1. 23 5月, 2014 7 次提交
  2. 22 5月, 2014 1 次提交
  3. 17 5月, 2014 6 次提交
  4. 16 5月, 2014 2 次提交
    • C
      Revert "arm64: Introduce execute-only page access permissions" · 5a0fdfad
      Catalin Marinas 提交于
      This reverts commit bc07c2c6.
      
      While the aim is increased security for --x memory maps, it does not
      protect against kernel level reads. Until SECCOMP is implemented for
      arm64, revert this patch to avoid giving a false idea of execute-only
      mappings.
      Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
      5a0fdfad
    • C
      Merge tag 'for-3.16' of git://git.linaro.org/people/ard.biesheuvel/linux-arm into upstream · cf5c95db
      Catalin Marinas 提交于
      FPSIMD register bank context switching and crypto algorithms
      optimisations for arm64 from Ard Biesheuvel.
      
      * tag 'for-3.16' of git://git.linaro.org/people/ard.biesheuvel/linux-arm:
        arm64/crypto: AES-ECB/CBC/CTR/XTS using ARMv8 NEON and Crypto Extensions
        arm64: pull in <asm/simd.h> from asm-generic
        arm64/crypto: AES in CCM mode using ARMv8 Crypto Extensions
        arm64/crypto: AES using ARMv8 Crypto Extensions
        arm64/crypto: GHASH secure hash using ARMv8 Crypto Extensions
        arm64/crypto: SHA-224/SHA-256 using ARMv8 Crypto Extensions
        arm64/crypto: SHA-1 using ARMv8 Crypto Extensions
        arm64: add support for kernel mode NEON in interrupt context
        arm64: defer reloading a task's FPSIMD state to userland resume
        arm64: add abstractions for FPSIMD state manipulation
        asm-generic: allow generic unaligned access if the arch supports it
      
      Conflicts:
      	arch/arm64/include/asm/thread_info.h
      cf5c95db
  5. 15 5月, 2014 7 次提交
  6. 12 5月, 2014 5 次提交
  7. 10 5月, 2014 8 次提交
  8. 09 5月, 2014 4 次提交
    • S
      arm64: mm: Create gigabyte kernel logical mappings where possible · 206a2a73
      Steve Capper 提交于
      We have the capability to map 1GB level 1 blocks when using a 4K
      granule.
      
      This patch adjusts the create_mapping logic s.t. when mapping physical
      memory on boot, we attempt to use a 1GB block if both the VA and PA
      start and end are 1GB aligned. This both reduces the levels of lookup
      required to resolve a kernel logical address, as well as reduces TLB
      pressure on cores that support 1GB TLB entries.
      Signed-off-by: NSteve Capper <steve.capper@linaro.org>
      Tested-by: NJungseok Lee <jays.lee@samsung.com>
      [catalin.marinas@arm.com: s/prot_sect_kernel/PROT_SECT_NORMAL_EXEC/]
      Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
      206a2a73
    • B
      arm64: Make atomic64_t() return "long", not "long long" · ba6bf8c8
      Bjorn Helgaas 提交于
      arm64 sets CONFIG_64BIT=y and hence uses the "long counter" atomic64_t
      definition from include/linux/types.h.  Make atomic64_read() return "long",
      not "long long".
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
      ba6bf8c8
    • C
      arm64: Clean up the default pgprot setting · a501e324
      Catalin Marinas 提交于
      The primary aim of this patchset is to remove the pgprot_default and
      prot_sect_default global variables and rely strictly on predefined
      values. The original goal was to be able to run SMP kernels on UP
      hardware by not setting the Shareability bit. However, it is unlikely to
      see UP ARMv8 hardware and even if we do, the Shareability bit is no
      longer assumed to disable cacheable accesses.
      
      A side effect is that the device mappings now have the Shareability
      attribute set. The hardware, however, should ignore it since Device
      accesses are always Outer Shareable.
      
      Following the removal of the two global variables, there is some PROT_*
      macro reshuffling and cleanup, including the __PAGE_* macros (replaced
      by PAGE_*).
      Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
      Acked-by: NWill Deacon <will.deacon@arm.com>
      a501e324
    • C
      arm64: Introduce execute-only page access permissions · bc07c2c6
      Catalin Marinas 提交于
      The ARMv8 architecture allows execute-only user permissions by clearing
      the PTE_UXN and PTE_USER bits. The kernel, however, can still access
      such page, so execute-only page permission does not protect against
      read(2)/write(2) etc. accesses. Systems requiring such protection must
      implement/enable features like SECCOMP.
      
      This patch changes the arm64 __P100 and __S100 protection_map[] macros
      to the new __PAGE_EXECONLY attributes. A side effect is that
      pte_valid_user() no longer triggers for __PAGE_EXECONLY since PTE_USER
      isn't set. To work around this, the check is done on the PTE_NG bit via
      the pte_valid_ng() macro. VM_READ is also checked now for page faults.
      Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
      bc07c2c6