1. 02 5月, 2013 3 次提交
  2. 11 4月, 2013 2 次提交
    • T
      OMAPDSS: DPI: widen the pck search when using dss fck · 2c6360fb
      Tomi Valkeinen 提交于
      When not using DSI PLL to generate the pixel clock, but DSS FCK, the
      possible pixel clock rates are rather limited. DSS FCK is currently used
      on OMAP2 and OMAP3.
      
      When using Beagleboard with a monitor that supports high resolutions,
      the clock rates do not match (at least for me) for the monitor's pixel
      clocks within the current threshold in the code, which is +/- 1MHz.
      
      This patch widens the search up to +/- 15MHz. The search is done in
      steps, i.e. it first tries to find a rather exact clock, than a bit less
      exact, etc. so this should not change the cases where a clock was
      already found.
      Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
      2c6360fb
    • T
      OMAPDSS: fix dss_fck clock rate rounding · 648a55e1
      Tomi Valkeinen 提交于
      DSS func clock is calculated with prate / div * m. However, the current
      omapdss code calculates it with prate * m / div, which yields a slightly
      different result when there's a remainder. For example, 432000000 / 14 *
      2 = 61714284, but 432000000 * 2 / 14 = 61714285.
      
      In addition to that, the clock framework wants the clock rate given with
      clk_set_rate to be higher than the actual (truncated) end result. So, if
      prate is 432000000, and div is 14, the real result is 30857142.8571...
      We need to call clk_set_rate with 30857143, which gives us a clock of
      30857142. That's why we need to use DIV_ROUND_UP() when calling
      clk_set_rate.
      
      This patch fixes the clock calculation.
      Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
      648a55e1
  3. 10 4月, 2013 8 次提交
  4. 03 4月, 2013 27 次提交