Add support for an MDIO bus multiplexer controlled by a simple memory-mapped
device, like an FPGA.  The device must be memory-mapped and contain only
8-bit registers (which keeps things simple).

Tested on a Freescale P5020DS board which uses the "PIXIS" FPGA attached
to the localbus.
Signed-off-by: NTimur Tabi <timur@freescale.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Add a driver for BCM8706 and BCM8727 devices.  These are a 10Gig PHYs
which use MII_ADDR_C45 addressing.  They are always 10G full duplex, so
there is no autonegotiation.  All we do is report link state and send
interrupts when it changes.

If the PHY has a device tree of_node associated with it, the
"broadcom,c45-reg-init" property is used to supply register
initialization values when config_init() is called.
Signed-off-by: NDavid Daney <david.daney@cavium.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

The GPIO pins select which sub bus is connected to the master.

Initially tested with an sn74cbtlv3253 switch device wired into the
MDIO bus.
Signed-off-by: NDavid Daney <david.daney@cavium.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

This patch adds a somewhat generic framework for MDIO bus
multiplexers.  It is modeled on the I2C multiplexer.

The multiplexer is needed if there are multiple PHYs with the same
address connected to the same MDIO bus adepter, or if there is
insufficient electrical drive capability for all the connected PHY
devices.

Conceptually it could look something like this:

                   ------------------
                   | Control Signal |
                   --------+---------
                           |
 ---------------   --------+------
 | MDIO MASTER |---| Multiplexer |
 ---------------   --+-------+----
                     |       |
                     C       C
                     h       h
                     i       i
                     l       l
                     d       d
                     |       |
     ---------       A       B   ---------
     |       |       |       |   |       |
     | PHY@1 +-------+       +---+ PHY@1 |
     |       |       |       |   |       |
     ---------       |       |   ---------
     ---------       |       |   ---------
     |       |       |       |   |       |
     | PHY@2 +-------+       +---+ PHY@2 |
     |       |                   |       |
     ---------                   ---------

This framework configures the bus topology from device tree data.  The
mechanics of switching the multiplexer is left to device specific
drivers.

The follow-on patch contains a multiplexer driven by GPIO lines.
Signed-off-by: NDavid Daney <david.daney@cavium.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Signed-off-by: NHeiko Schocher <hs@denx.de>
Signed-off-by: NAnatolij Gustschin <agust@denx.de>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Signed-off-by: NFrederic Lambert <frdrc66@gmail.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

This patch adds support for the PTP clock found on the DP83640.
The basic clock operations and one external time stamp have
been implemented.
Signed-off-by: NRichard Cochran <richard.cochran@omicron.at>
Signed-off-by: NJohn Stultz <john.stultz@linaro.org>

This is the first version of phy driver from Micrel Inc.
Signed-off-by: NDavid J. Choi <david.choi@micrel.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

The Octeon SOC has two types of Ethernet ports, each type with its own
driver.  However, the PHYs for all the ports are controlled by a
common MDIO bus.  Because the mdio driver is not associated with a
particular driver, but is instead a system level resource, we create s
stand-alone driver for it.

As for the driver, we put the register definitions in
arch/mips/include/asm/octeon where most of the other Octeon register
definitions live.  This is a platform driver with the platform device
for "mdio-octeon" being registered in the platform startup code.
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
Acked-by: NDavid S. Miller <davem@davemloft.net>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NMaxime Bizon <mbizon@freebox.fr>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

 drivers/net/phy/Kconfig   |    6 ++
 drivers/net/phy/Makefile  |    1
 drivers/net/phy/bcm63xx.c |  132 ++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 139 insertions(+)
 create mode 100644 drivers/net/phy/bcm63xx.c
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Adds LSI ET1011C PHY driver. 
This driver is used by TI DM646x EVM.
Signed-off-by: NChaithrika U S <chaithrika@ti.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

This patch adds the STMicroelectronics ste10xp PHY device driver.
It supports both the ste100p and the ste101p devices.

Suspend/resume alredy added.
Signed-off-by: NGiuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

This patch adds the PHY device driver for the National Semiconductor
DP83865 Gig PHYTER.
Signed-off-by: NGiuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Signed-off-by: NPaulius Zaleckas <paulius.zaleckas@teltonika.lt>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

This patch adds an MDIO bitbang driver that uses the GPIO library and its
OF bindings to access the bus I/Os.
Signed-off-by: NLaurent Pinchart <laurentp@cse-semaphore.com>
Signed-off-by: NJeff Garzik <jgarzik@redhat.com>

this PHY present on the MPC8315E and MPC837xE RDB boards.
Signed-off-by: NJohnson Leung <r58129@freescale.com>
Signed-off-by: NKevin Lam <r43770@freescale.com>
Signed-off-by: NJoe D'Abbraccio <ljd015@freescale.com>
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Previously, bitbanged MDIO was only supported in individual
hardware-specific drivers.  This code factors out the higher level
protocol implementation, reducing the hardware-specific portion to
functions setting direction, data, and clock.
Signed-off-by: NScott Wood <scottwood@freescale.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

The ICPlus IP175C sports a 100Mbit/s 4-port switch in addition
to a dedicated 100Mbit/s WAN port.
Signed-off-by: NMichael Barkowski <michael.barkowski@freescale.com>
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

 This patch adds support for interrupt-driven operation of the Broadcom
Gigabit Ethernet PHYs.  I have included device IDs for the parts used on
Broadcom SiByte evaluation boards; more can be added as a need arises.
They are apparently generally software-compatible with one another.
Signed-off-by: NMaciej W. Rozycki <macro@linux-mips.org>

patch-mips-2.6.18-20060920-broadcom-phy-15
Signed-off-by: NJeff Garzik <jeff@garzik.org>

This makes it possible for HW PHY-less boards to utilize PAL goodies.  Generic
routines to connect to fixed PHY are provided, as well as ability to specify
software callback that fills up link, speed, etc.  information into PHY
descriptor (the latter feature not tested so far).
Signed-off-by: NVitaly Bordug <vbordug@ru.mvista.com>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

Signed-off-by: NKriston Carson <KristonCarson@freescale.com>
Signed-off-by: NXianghua Xiao <x.xiao@freescale.com>
Signed-off-by: NJon Loeliger <jdl@freescale.com>
Acked-by: NJeff Garzik <jeff@garzik.org>
Signed-off-by: NPaul Mackerras <paulus@samba.org>

new SMSC LAN83C185 10BaseT/100BaseTX PHY driver for the PHY subsystem
Signed-off-by: NHerbert Valerio Riedel <hvr@gnu.org>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

This patch adds back the code that was taken out, thus re-enabling:

* The PHY Layer to initialize without crashing
* Drivers to actually connect to PHYs
* The entire PHY Control Layer

This patch is used by the gianfar driver, and other drivers which are in
development.
Signed-off-by: NAndy Fleming <afleming@freescale.com>
Signed-off-by: NJeff Garzik <jgarzik@pobox.com>

Includes fixes for problems noted by Adrian Bunk, Andrew Morton,
and one other person lost in the annals of history (and email folders).

ethernet drivers to remain as ignorant as is reasonable of the connected
PHY's design and operation details.
Signed-off-by: NAndy Fleming <afleming@freescale.com>
Signed-off-by: NJeff Garzik <jgarzik@pobox.com>