- 09 4月, 2013 17 次提交
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由 Sourav Poddar 提交于
Booting 3.8-rc6 on omap4 panda results in the following error [ 0.444427] omap_i2c 48070000.i2c: did not get pins for i2c error: -19 [ 0.445770] omap_i2c 48070000.i2c: bus 0 rev0.11 at 400 kHz [ 0.473937] omap_i2c 48072000.i2c: did not get pins for i2c error: -19 [ 0.474670] omap_i2c 48072000.i2c: bus 1 rev0.11 at 400 kHz [ 0.474822] omap_i2c 48060000.i2c: did not get pins for i2c error: -19 [ 0.476379] omap_i2c 48060000.i2c: bus 2 rev0.11 at 100 kHz [ 0.477294] omap_i2c 48350000.i2c: did not get pins for i2c error: -19 [ 0.477996] omap_i2c 48350000.i2c: bus 3 rev0.11 at 400 kHz [ 0.483398] Switching to clocksource 32k_counter This happens because omap4 panda dts file is not adapted to use i2c through pinctrl framework. Populating i2c pinctrl data to get rid of the error. Tested on omap4460 panda with 3.8-rc6 kernel. Signed-off-by: NSourav Poddar <sourav.poddar@ti.com> Reported-by: NLuciano Coelho <coelho@ti.com> Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>
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由 Sourav Poddar 提交于
Booting 3.8-rc6 on omap 5430evm results in the following error omap_i2c 48070000.i2c: did not get pins for i2c error: -19 [ 1.024261] omap_i2c 48070000.i2c: bus 0 rev0.12 at 100 kHz [ 1.030181] omap_i2c 48072000.i2c: did not get pins for i2c error: -19 [ 1.037384] omap_i2c 48072000.i2c: bus 1 rev0.12 at 400 kHz [ 1.043762] omap_i2c 48060000.i2c: did not get pins for i2c error: -19 [ 1.050964] omap_i2c 48060000.i2c: bus 2 rev0.12 at 100 kHz [ 1.056823] omap_i2c 4807a000.i2c: did not get pins for i2c error: -19 [ 1.064025] omap_i2c 4807a000.i2c: bus 3 rev0.12 at 400 kHz This happens because omap5 dts file is not adapted to use i2c through pinctrl framework. Populating i2c pinctrl data to get rid of the error. Tested on omap5430 evm with 3.8-rc6 kernel. Signed-off-by: NSourav Poddar <sourav.poddar@ti.com> Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>
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由 Florian Vaussard 提交于
Add the needed sections to enable audio support on Overo. Signed-off-by: NFlorian Vaussard <florian.vaussard@epfl.ch> Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>
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由 Sourav Poddar 提交于
Booting 3.8-rc6 on omap 4430sdp results in the following error omap_i2c 48070000.i2c: did not get pins for i2c error: -19 [ 1.024261] omap_i2c 48070000.i2c: bus 0 rev0.12 at 100 kHz [ 1.030181] omap_i2c 48072000.i2c: did not get pins for i2c error: -19 [ 1.037384] omap_i2c 48072000.i2c: bus 1 rev0.12 at 400 kHz [ 1.043762] omap_i2c 48060000.i2c: did not get pins for i2c error: -19 [ 1.050964] omap_i2c 48060000.i2c: bus 2 rev0.12 at 100 kHz [ 1.056823] omap_i2c 4807a000.i2c: did not get pins for i2c error: -19 [ 1.064025] omap_i2c 4807a000.i2c: bus 3 rev0.12 at 400 kHz This happens because omap4 dts file is not adapted to use i2c through pinctrl framework. Populating i2c pinctrl data to get rid of the error. Tested on omap4430 sdp with 3.8-rc6 kernel. Signed-off-by: NSourav Poddar <sourav.poddar@ti.com> Reported-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>
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由 Florian Vaussard 提交于
Convert the on-board LED connected to the TWL4030 (LEDB) to use pwm-leds. Signed-off-by: NFlorian Vaussard <florian.vaussard@epfl.ch> Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>
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由 Peter Ujfalusi 提交于
Section to describe the backlight for the LCD panels. Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>
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由 Peter Ujfalusi 提交于
Sections to describe the pwm-leds in the system. Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>
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由 Peter Ujfalusi 提交于
We have proper driver stack to handle the pmu_stat LED which is connected PWMB of twl4030. Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>
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由 Peter Ujfalusi 提交于
Enable support for the PWMs and LED as PWM drivers. Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>
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由 Peter Ujfalusi 提交于
Enable support for the PWMs and LEDs as PWM drivers. Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>
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由 AnilKumar Ch 提交于
Add a new address space/memory resource to d_can device tree node. D_CAN RAM initialization is achieved through RAMINIT register which is part of AM33XX control module address space. D_CAN RAM init or de-init should be done by writing instance corresponding value to control module register. Till we have a separate control module driver to write to control module, d_can driver will handle the register writes to control module by itself. So a new address space to represent this control module register is added to d_can driver. Signed-off-by: NAnilKumar Ch <anilkumar@ti.com> Acked-by: NMarc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>
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由 AnilKumar Ch 提交于
Add d_can instances to aliases node to get the D_CAN instance number from the driver. To initialize D_CAN message RAM, corresponding instance number is required. To initialize instance 0 message RAM then 0x1 should be written and for instance 1 message RAM, 0x2 should be written to control module register. With device-tree framework ip instance number is "-1" by default for all instances. To get device id/instance number then modules should be added to DT "aliases" node. of_alias_get_id() gives the device id number based on number of alias nodes present in "aliases node". Signed-off-by: NAnilKumar Ch <anilkumar@ti.com> Acked-by: NMarc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>
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由 Matthias Brugger 提交于
This is a follow-up to Javier Martinez effort adding initial device tree support to IGEP technology devices [1]. It adds uart1 and uart2 bindings to the generic dtsi for the IGEP boards. [1] http://www.spinics.net/lists/linux-omap/msg83409.htmlSigned-off-by: NMatthias Brugger <matthias.bgg@gmail.com> Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>
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由 Javier Martinez Canillas 提交于
ISEE IGEP COM Module is an TI OMAP3 SoC computer on module. This patch adds an initial device tree support to boot an IGEP COM Module from the MMC/SD. Signed-off-by: NJavier Martinez Canillas <javier.martinez@collabora.co.uk> Tested-by: NEnric Balletbo i Serra <eballetbo@gmail.com> [b-cousson@ti.com: Update the Makefile for 3.8-rc2] Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>
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由 Javier Martinez Canillas 提交于
ISEE IGEPv2 is an TI OMAP3 SoC based embedded board. This patch adds an initial device tree support to boot an IGEPv2 from the MMC/SD. Currently is working everything that is supported by DT on OMAP3 SoCs (MMC/SD, GPIO LEDs, EEPROM, TWL4030 audio). Signed-off-by: NJavier Martinez Canillas <javier.martinez@collabora.co.uk> Tested-by: NEnric Balletbo i Serra <eballetbo@gmail.com> [benoit.cousson@linaro.org: Update the Makefile for 3.8-rc2] Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>
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由 Javier Martinez Canillas 提交于
Add a generic .dtsi device tree source file for the common characteristics across IGEP Technology devices. Signed-off-by: NJavier Martinez Canillas <javier.martinez@collabora.co.uk> Acked-by: NMatthias Brugger <matthias.bgg@gmail.com> Tested-by: NEnric Balletbo i Serra <eballetbo@gmail.com> Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>
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由 AnilKumar Ch 提交于
Rename I2C and GPIO nodes according to AM33XX TRM. According to AM33XX TRM device instances are starting from "0" like i2c0, i2c1 and i2c3. Signed-off-by: NPantelis Antoniou <panto@antoniou-consulting.com> [panto@antoniou-consulting.com: initial patch by pantelis's] Signed-off-by: NAnilKumar Ch <anilkumar@ti.com> Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>
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- 03 4月, 2013 3 次提交
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由 Roger Quadros 提交于
Provide RESET and Power regulators for the USB PHY, the USB Host port mode and the PHY device. Also provide pin multiplexer information for USB host pins. CC: Benoît Cousson <b-cousson@ti.com> Signed-off-by: NRoger Quadros <rogerq@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Roger Quadros 提交于
Adds device nodes for HS USB Host module, TLL module, OHCI and EHCI controllers. CC: Benoît Cousson <b-cousson@ti.com> Signed-off-by: NRoger Quadros <rogerq@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Roger Quadros 提交于
Adds device nodes for HS USB Host module, TLL module, OHCI and EHCI controllers. CC: Benoît Cousson <b-cousson@ti.com> Signed-off-by: NRoger Quadros <rogerq@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 23 3月, 2013 1 次提交
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由 Laxman Dewangan 提交于
Fix typo on register address of slink3 controller where register address is wrongly set as 0x7000d480 but it is 0x7000d800. Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com> Cc: <stable@vger.kernel.org> Signed-off-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NArnd Bergmann <arnd@arndb.de>
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- 13 3月, 2013 2 次提交
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由 Richard Genoud 提交于
There was only chip enable and readdy/busy pins for the nand controller. This add the rest of the pins. pinctrl_nand_16bits contains the specific muxes for 16 bits NANDs. Signed-off-by: NRichard Genoud <richard.genoud@gmail.com> Acked-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
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由 Richard Genoud 提交于
Comments on NAND pins where inverted. Signed-off-by: NRichard Genoud <richard.genoud@gmail.com> Acked-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
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- 12 3月, 2013 2 次提交
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由 Arnd Bergmann 提交于
The ab8500 device is a child of the prcmu device, which is a memory mapped bus device, whose children are addressable using physical memory addresses, not using mailboxes, so a mailbox number in the ab8500 node cannot be parsed by DT. Nothing uses this number, since it was only introduced as part of the failed attempt to clean up prcmu mailbox handling, and we can simply remove it. Signed-off-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NSamuel Ortiz <sameo@linux.intel.com>
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由 Padmavathi Venna 提交于
This patch adds #dma-cells property to PL330 DMA controller nodes for supporting generic dma dt bindings on SOCFPGA platform. #dma-channels and #dma-requests are not required now but added in advance. Signed-off-by: NPadmavathi Venna <padma.v@samsung.com> Signed-off-by: NArnd Bergmann <arnd@arndb.de>
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- 09 3月, 2013 8 次提交
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由 Thomas Petazzoni 提交于
The orion5x-lacie-ethernet-disk-mini-v2.dts file was using "marvell-orion5x-88f5182" as a compatible string, while it should have been "marvell,orion5x-88f5182". Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Thomas Petazzoni 提交于
There is no need to have a #address-cells property in the MPIC Device Tree node, and more than that, having it confuses the of_irq_map_raw() logic, which will be used by the Marvell PCIe driver. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Heikki Krogerus 提交于
Setting the reg-io-width to 1 byte represents more accurate description of the HW. This will fix an issue where UART driver causes kernel panic during bootup. Gregory CLEMENT traced the issue to autoconfig() in 8250.c, where the existence of FIFO is checked from UART_IIR register. The register is now read as 32-bit value as the reg-io-width is set to 4-bytes. The retuned value seems to contain bogus data for bits 31:8, causing the issue. Signed-off-by: NHeikki Krogerus <heikki.krogerus@linux.intel.com> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Masami Hiramatsu <masami.hiramatsu.pt@hitachi.com> Tested-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Tested-by: NMasami Hiramatsu <masami.hiramatsu.pt@hitachi.com> Tested-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Jean-Francois Moine 提交于
The commit: 48be9ac9 ARM: Dove: split legacy and DT setup removed the RTC initialization. This patch re-enables the RTC via the DT. Signed-off-by: NJean-François Moine <moinejf@free.fr> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Florian Fainelli 提交于
This patch modifies the Armada 370 Reference Design DTS file to enable support for the two USB ports found on this board. Signed-off-by: NFlorian Fainelli <florian@openwrt.org> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Andrew Lunn 提交于
The Marvell RTC on Kirkwood makes use of the runit clock. Ensure the driver clk_prepare_enable() this clock, otherwise there is a danger the SoC will lockup when accessing RTC registers with the clock disabled. Reported-by: NSimon Baatz <gmbnomis@gmail.com> Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Tested-by: NSimon Baatz <gmbnomis@gmail.com> Cc: <stable@vger.kernel.org> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Andrew Lunn 提交于
The kirkwood SoC GPIO cores use the runit clock. Add code to clk_prepare_enable() runit, otherwise there is a danger of locking up the SoC by accessing the GPIO registers when runit clock is not ticking. Reported-by: NSimon Baatz <gmbnomis@gmail.com> Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Tested-by: NSimon Baatz <gmbnomis@gmail.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Cc: <stable@vger.kernel.org> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Jason Cooper 提交于
When DT support for kirkwood was first introduced, there was no clock infrastructure. As a result, we had to manually pass the clock-frequency to the driver from the device node. Unfortunately, on kirkwood, with minimal config or all module configs, clock-frequency breaks booting because of_serial doesn't consume the gate_clk when clock-frequency is defined. The end result on kirkwood is that runit gets gated, and then the boot fails when the kernel tries to write to the serial port. Fix the issue by removing the clock-frequency parameter from all kirkwood dts files. Booted on dreamplug without earlyprintk and successfully logged in via ttyS0. Reported-by: NSimon Baatz <gmbnomis@gmail.com> Tested-by: NSimon Baatz <gmbnomis@gmail.com> Cc: <stable@vger.kernel.org> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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- 07 3月, 2013 2 次提交
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由 Padmavathi Venna 提交于
This patch adds #dma-cells property to PL330 DMA controller nodes for supporting generic dma dt bindings on samsung exynos platforms. #dma-channels and #dma-requests are not required now but added in advance. Signed-off-by: NPadmavathi Venna <padma.v@samsung.com> Acked-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Jonathan Austin 提交于
Before jumping to (position independent) C-code from the decompressor's assembler world we set-up the C environment. This setup currently does not set r9, which for arm-none-uclinux-uclibceabi toolchains is by default expected to be the PIC offset base register (IE should point to the beginning of the GOT). Currently, therefore, in order to build working kernels that use the decompressor it is necessary to use an arm-linux-gnueabi toolchain, or similar. uClinux toolchains cause a prefetch abort to occur at the beginning of the decompress_kernel function. This patch allows uClinux toolchains to build bootable zImages by forcing the -mno-single-pic-base option, which ensures that the location of the GOT is re-derived each time it is required, and r9 becomes free for use as a general purpose register. This has a small (4% in instruction terms) advantage over the alternative of setting r9 to point to the GOT before calling into the C-world. Signed-off-by: NJonathan Austin <jonathan.austin@arm.com> Acked-by: NNicolas Pitre <nico@linaro.org> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 05 3月, 2013 3 次提交
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由 Prashant Gaikwad 提交于
As DT support for clocks and smp_twd is enabled, add clock entry for smp_twd clock to DT. This fixes the following error while booting the kernel: smp_twd: clock not found -2 Signed-off-by: NPrashant Gaikwad <pgaikwad@nvidia.com> [swarren: include kernel log spew that this fixes] Signed-off-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NOlof Johansson <olof@lixom.net>
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由 Nishanth Menon 提交于
commit 5f300acd (ARM: 7152/1: distclean: Remove generated .dtb files) ensured that dtbs were cleaned up when they were in arch/arm/boot. However, with the following commit: commit 499cd829 (ARM: dt: change .dtb build rules to build in dts directory) make clean now leaves dtbs in arch/arm/boot/dts/ untouched. Include dts directory so that clean-files rule from arch/arm/boot/dts/Makefile is invoked when make clean is done. Cc: Dirk Behme <dirk.behme@de.bosch.com> CC: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: NNishanth Menon <nm@ti.com> Signed-off-by: NOlof Johansson <olof@lixom.net>
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由 Stephen Warren 提交于
BCM2835-ARM-Peripherals.pdf states that the I2C module's input clock is nominally 150MHz, and that value is currently reflected in bcm2835.dtsi. However, practical measurements show that the rate is actually 250MHz, and this agrees with various downstream kernels. Switch the I2C clock's frequency to 250MHz so that the generated bus clock rate is accurate. Signed-off-by: NStephen Warren <swarren@wwwdotorg.org> Signed-off-by: NOlof Johansson <olof@lixom.net>
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- 04 3月, 2013 1 次提交
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由 Shawn Guo 提交于
According to fsl,imx53-pinctrl.txt, the pin number of DISP1_DAT_21 should be 545, while 543 is IPU_CSI0_D_3. Along with the change, one duplication of DISP1_DAT_0 in disp1-grp1 is removed. Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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- 01 3月, 2013 1 次提交
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由 Florian Fainelli 提交于
The Armada 370 Reference Design board has one SD card slot, directly connected to the SDIO IP of the SoC, so we enable this IP. there are no GPIOs for card-detect and write-protect so we do not specify any. Signed-off-by: NFlorian Fainelli <florian@openwrt.org> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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