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  1. 01 6月, 2017 1 次提交
  3. 10 1月, 2017 1 次提交
  5. 02 11月, 2016 2 次提交
    • E
      clk: imx: improve precision of AV PLL to 1 Hz · c5a8045a
      由 Emil Lundmark 提交于 
      The audio and video PLLs are designed to have a precision of 1 Hz if some
conditions are met. The current implementation only allows a precision that
depends on the rate of the parent clock. E.g., if the parent clock is 24
MHz, the precision will be 24 Hz; or more generally the precision will be

    p / 10^6 Hz

where p is the parent clock rate. This comes down to how the register
values for the PLL's fractional loop divider are chosen.

The clock rate calculation for the PLL is

    PLL output frequency = Fref * (DIV_SELECT + NUM / DENOM)

or with a shorter notation

    r = p * (d + a / b)

In addition to all variables being integers, we also have the following
conditions:

    27 <= d <= 54

    -2^29 <= a <= 2^29-1
     0    <  b <= 2^30-1
    |a| < b

Here, d, a and b are register values for the fractional loop divider. We
want to chose d, a and b such that f(p, r) = p, i.e. f is our round_rate
function. Currently, d and b are chosen as

    d = r / p
    b = 10^6

hence we get the poor precision. And a is defined in terms of r, d, p and
b:

    a = (r - d * p) * b / p

I propose that if p <= 2^30-1 (i.e., the max value for b), we chose b as

    b = p

We can do this since

    |a| < b

    |(r - d * p) * b / p| < b

    |r - d * p| < p

Which have two solutions, one of them is when p < 0, so we can skip that
one. The other is when p > 0 and

    p * (d - 1) < r < p * (d + 1)

Substitute d = r / p:

    (r - p) < r < (r + p)  <=>  p > 0

So, as long as p > 0, we can chose b = p. This is a good choise for b since

    a = (r - d * p) * b / p
      = (r - d * p) * p / p
      = r - d * p

    r = p * (d + a / b)
      = p * d + p * a / b
      = p * d + p * a / p
      = p * d + a

and if d = r / p:

    a = r - d * p
      = r - r / p * p
      = 0

    r = p * d + a
      = p * d + 0
      = p * r / p
      = r

I reckon this is the intention by the design of the clock rate formula.
Signed-off-by: NEmil Lundmark <emil@limesaudio.com>
Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>
Acked-by: NShawn Guo <shawnguo@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
      c5a8045a
    • E
      clk: imx: fix integer overflow in AV PLL round rate · 5c2f117a
      由 Emil Lundmark 提交于 
      Since 'parent_rate * mfn' may overflow 32 bits, the result should be
stored using 64 bits.

The problem was discovered when trying to set the rate of the audio PLL
(pll4_post_div) on an i.MX6Q. The desired rate was 196.608 MHz, but
the actual rate returned was 192.000570 MHz. The round rate function should
have been able to return 196.608 MHz, i.e., the desired rate.

Fixes: ba7f4f55 ("clk: imx: correct AV PLL rate formula")
Cc: Anson Huang <b20788@freescale.com>
Signed-off-by: NEmil Lundmark <emil@limesaudio.com>
Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>
Acked-by: NShawn Guo <shawnguo@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
      5c2f117a
  7. 16 6月, 2016 1 次提交
  9. 13 6月, 2016 1 次提交
  11. 12 6月, 2016 1 次提交
    • A
      clk: imx: correct AV PLL rate formula · ba7f4f55
      由 Anson Huang 提交于 
      The audio/video PLL's rate calculation is as below in RM:

Fref * (DIV_SELECT + NUM / DENOM), in origin clk-pllv3's
code, below code is used:

(parent_rate * div) + ((parent_rate / mfd) * mfn

as it does NOT consider the float data using div, so below
formula should be used as a decent method:

(parent_rate * div) + ((parent_rate * mfn) / mfd)

and we also need to consider parent_rate * mfd may overflow
a 32 bit value, 64 bit value should be used.

After updating this formula, the dram PLL's rate is
1066MHz, which is correct, while the old formula gets
1056MHz.

[Aisheng: fix clk_pllv3_av_round_rate too]
Signed-off-by: NAnson Huang <b20788@freescale.com>
Signed-off-by: NDong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>
      ba7f4f55
  13. 27 4月, 2016 1 次提交
  15. 25 11月, 2015 1 次提交
  17. 21 7月, 2015 1 次提交
    • S
      clk: i.MX: Remove clk.h include · 663724f9
      由 Stephen Boyd 提交于 
      Clock provider drivers generally shouldn't include clk.h because
it's the consumer API. Remove the include here because this is a
provider driver.

Cc: Alexander Shiyan <shc_work@mail.ru>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
      663724f9
  19. 03 6月, 2015 3 次提交
  21. 05 1月, 2015 1 次提交
  23. 22 11月, 2014 1 次提交
  25. 16 9月, 2014 1 次提交
  27. 11 11月, 2013 3 次提交
    • S
      ARM: imx: set up pllv3 POWER and BYPASS sequentially · 43c9b9e8
      由 Shawn Guo 提交于 
      Currently, POWER and BYPASS bits are set up in a single write to pllv3
register.  This causes problem occasionally from the IPU/HDMI testing.
Let's follow FSL BSP code to set up POWER bit, relock, and then BYPASS
sequentially.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
      43c9b9e8
    • S
      ARM: imx: pllv3 needs relock in .set_rate() call · bc3b84da
      由 Shawn Guo 提交于 
      The pllv3 nees relock not only when powering up but also when rate
changes.  The patch creates a helper function clk_pllv3_wait_lock() and
moves the relock code from clk_pllv3_prepare() into there, so that
both .prepare() and .set_rate() hooks of pllv3 can call into the helper
for relocking.

Since relock is only needed when PLL is powered up while clk_set_rate()
could be called before clk is prepared, we need to add a check in
clk_pllv3_wait_lock() to skip the relock if PLL is not powered.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
      bc3b84da
    • S
      ARM: imx: add sleep for pllv3 relock · 322503a1
      由 Shawn Guo 提交于 
      The pllv3 relock time varies in the range of 50us ~ 500us, depending on
the specific PLL type, e.g. 50us for ARM PLL and 450us for Audio/Video
PLL.  Let's add a usleep_range() call instead of doing busy wait during
relock.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
      322503a1
  29. 16 8月, 2013 1 次提交
  31. 17 6月, 2013 1 次提交
  33. 22 11月, 2012 2 次提交
    • S
      ARM i.MX6: remove gate_mask from pllv3 · 2b254693
      由 Sascha Hauer 提交于 
      Now that the additional enable bits in the enet PLL are handled
as gates, the gate_mask is identical for all plls. Remove the
gate_mask from the code and use the BM_PLL_ENABLE bit for
enabling/disabling the PLL.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Acked-by: NShawn Guo <shawn.guo@linaro.org>
      2b254693
    • S
      ARM i.MX6: Fix ethernet PLL clocks · 7a04092c
      由 Sascha Hauer 提交于 
      In current code the ethernet PLL is not handled correctly. The PLL runs at 500MHz
and has different outputs. Only the enet reference clock is implemented. This
patch changes the PLL so that it outputs 500MHz and adds the additional outputs
as dividers. This now matches the datasheet which says:

> This PLL synthesizes a low jitter clock from 24 MHz reference clock.
> The PLL outputs a 500 MHz clock. The reference clocks generated by this PLL are:
>  • Ref_PCIe = 125 MHz
>  • Ref_SATA = 100 MHz
>  • Ref_ethernet, which is configurable based on the PLL_ENET[1:0] register field.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Acked-by: NShawn Guo <shawn.guo@linaro.org>
      7a04092c
  35. 02 5月, 2012 1 次提交