1. 28 9月, 2016 1 次提交
  2. 22 9月, 2016 1 次提交
  3. 19 8月, 2016 1 次提交
  4. 17 8月, 2016 1 次提交
    • K
      igb: fix adjusting PTP timestamps for Tx/Rx latency · 0066c8b6
      Kshitiz Gupta 提交于
      Fix PHY delay compensation math in igb_ptp_tx_hwtstamp() and
      igb_ptp_rx_rgtstamp. Add PHY delay compensation in
      igb_ptp_rx_pktstamp().
      
      In the IGB driver, there are two functions that retrieve timestamps
      received by the PHY - igb_ptp_rx_rgtstamp() and igb_ptp_rx_pktstamp().
      The previous commit only changed igb_ptp_rx_rgtstamp(), and the change
      was incorrect.
      
      There are two instances in which PHY delay compensations should be
      made:
      
      - Before the packet transmission over the PHY, the latency between
        when the packet is timestamped and transmission of the packets,
        should be an add operation, but it is currently a subtract.
      
      - After the packets are received from the PHY, the latency between
        the receiving and timestamping of the packets should be a subtract
        operation, but it is currently an add.
      Signed-off-by: NKshitiz Gupta <kshitiz.gupta@ni.com>
      Fixes: 3f544d2a (igb: adjust ptp timestamps for tx/rx latency)
      Tested-by: NAaron Brown <aaron.f.brown@intel.com>
      Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
      0066c8b6
  5. 30 6月, 2016 4 次提交
  6. 14 5月, 2016 2 次提交
  7. 25 2月, 2016 1 次提交
    • R
      igb: add conditions for I210 to generate periodic clock output · 569f3b3d
      Roland Hii 提交于
      In general case the maximum supported half cycle time of the synchronized
      output clock is 70msec. Slower half cycle time than 70msec can be
      programmed also as long as the output clock is synchronized to whole
      seconds, useful specifically for generating a 1Hz clock.
      
      Permitted values for the clock half cycle time are: 125,000,000 decimal,
      250,000,000 decimal and 500,000,000 decimal (equals to 125msec, 250msec
      and 500msec respectively).
      
      Before this patch, only the half cycle time of less than or equal to 70msec
      uses the I210 clock output function. This patch adds additional conditions
      when half cycle time is equal to 125msec or 250msec or 500msec to use
      clock output function.
      
      Under other conditions, interrupt driven target time output events method
      is still used to generate the desired clock output.
      Signed-off-by: NRoland Hii <roland.king.guan.hii@intel.com>
      Tested-by: NAaron Brown <aaron.f.brown@intel.com>
      Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
      569f3b3d
  8. 05 10月, 2015 1 次提交
  9. 19 8月, 2015 1 次提交
  10. 12 6月, 2015 1 次提交
  11. 01 4月, 2015 2 次提交
  12. 09 3月, 2015 1 次提交
  13. 06 3月, 2015 2 次提交
  14. 23 1月, 2015 3 次提交
  15. 03 1月, 2015 1 次提交
  16. 01 1月, 2015 1 次提交
  17. 31 12月, 2014 1 次提交
  18. 11 6月, 2014 1 次提交
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  22. 28 3月, 2014 1 次提交
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  25. 27 2月, 2014 2 次提交
  26. 22 8月, 2013 1 次提交
  27. 19 4月, 2013 2 次提交
  28. 26 3月, 2013 1 次提交
  29. 18 1月, 2013 2 次提交