The insert_nop function is added to amdgpu_ring_funcs structure as
well as the default implementation
Signed-off-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>

The problem now is that we don't necessarily call amdgpu_ib_get()
in some error paths and so work with uninitialized data.

Better require that the memory is already zeroed.

v2: better commit message
Signed-off-by: NChristian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com> (v1)
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>

fix fence is released when pass to **fence sometimes.
add reference for it.
Signed-off-by: NChunming Zhou <david1.zhou@amd.com>
Reviewed-by: NChristian K?nig <christian.koenig@amd.com>

every sbumission should be able to get a fence.
Signed-off-by: NChunming Zhou <david1.zhou@amd.com>
Reviewed-by: NChristian K?nig <christian.koenig@amd.com>
Reviewed-by: NJammy Zhou <jammy.zhou@amd.com>

Signed-off-by: NChunming Zhou <david1.zhou@amd.com>
Reviewed-by: NChristian K?nig <christian.koenig@amd.com>
Reviewed-by: NJammy Zhou <jammy.zhou@amd.com>

Signed-off-by: NChunming Zhou <david1.zhou@amd.com>
Reviewed-by: NChristian K?nig <christian.koenig@amd.com>

v2: agd5f: fix the rb setup.
Signed-off-by: NDavid Zhang <david1.zhang@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>

Make the definitions common for all driver components

v2: fix kfd
Signed-off-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>

This reverts commit 78ad5cdd.
This commit breaks dpm and suspend/resume on CZ.

The fw_version and feature_verion should be set correctly when the
firmwares are loaded by SMU on Tonga/Carrzio/Iceland
Signed-off-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>

Expose feature version to user space for RLC/MEC/MEC2 ucode as well

v2: fix coding style
Signed-off-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>

Always set num_rbs to 2 for CZ.  The 1 RB parts are often harvest
configs.  The will get sorted out in mesa when we program
PA_SC_RASTER_CONFIG[_1].
Acked-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

compute ring didn't use const engine byfar, so ignore CE things in
compute routine
Signed-off-by: Nmonk.liu <monk.liu@amd.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>

Always respect the harvest configuration as is.
Acked-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This patch is to resolve compute hang at resume time.

v2: (agd5f) squash in second fix
Signed-off-by: NSonny Jiang <sonny.jiang@amd.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>

Signed-off-by: NBen Goz <ben.goz@amd.com>
Acked-by: NOded Gabbay <oded.gabbay@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

v2: add missing MTYPE_NONCACHED enum
Signed-off-by: NBen Goz <ben.goz@amd.com>
Acked-by: NOded Gabbay <oded.gabbay@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Reviewed-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NDavid Zhang <david1.zhang@amd.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>

Need to adjust the number of CUs and RBs.

v2: get proper values
Reviewed-by: NChristian König <christian.koenig@amd.com>
Reviewed-by: NSamuel Li <samuel.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

amdgpu submits both kernel and user fences, but just need one interrupt,
disable user fence interrupt and don't effect user fence.

v2: fix merge error
Signed-off-by: NChunming Zhou <david1.zhou@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>

Provide this information to usermode drivers.  We were previously
missing this info.
Signed-off-by: NKen Wang <Qingqing.Wang@amd.com>
Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>

Add a query for the CE ram size.  User mode drivers
will want to use this to determine how much size
of the cache on the CE.
Signed-off-by: NKen Wang <Qingqing.Wang@amd.com>
Reviewd-by: NJammy Zhou <Jammy.Zhou@amd.com>

We had forgotten to register the callback.
Signed-off-by: Nmonk.liu <monk.liu@amd.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>
Reviewed-by: Njammy zhou <jammy.zhou@amd.com>

Leave that at the values set during init.  No need to update
them repeatedly.
Signed-off-by: Nmonk.liu <monk.liu@amd.com>
Signed-off-by: NDavid Zhang <david1.zhang@amd.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>
Reviewed-by: NJammy Zhou <jammy.zhou@amd.com>

The structure is renamed and moved to amd_shared.h to make
the component independent.  This makes it easier to add
new components in the future.

v2: fix include path
Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: Nyanyang1 <young.yang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

v2: keep using radeon folder for CIK
Signed-off-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>

Properly protect the state and also handle submission failures.
Signed-off-by: NChristian König <christian.koenig@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NMonk Liu <monk.liu@amd.com>

Signed-off-by: NChristian König <christian.koenig@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NMonk Liu <monk.liu@amd.com>

The CE preamble IB can be dropped for the same context

v2: use the flags directly
v3: remove 'CE' for potential preamble usage by other rings
Signed-off-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>

Signed-off-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>

Set up the CP and SDMA for proper unaligned memory access.
Required for OpenCL 2.x

v2: udpate commit message
Signed-off-by: NJack Xiao <Jack.Xiao@amd.com>
Reviewed-by: NMonk Liu <monk.liu@amd.com>
Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>

This adds initial support for VI asics.  This
includes Iceland, Tonga, and Carrizo.  Our inital
focus as been Carrizo, so there are still gaps in
support for Tonga and Iceland, notably power
management.
Acked-by: NChristian König <christian.koenig@amd.com>
Acked-by: NJammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>