- 04 3月, 2010 3 次提交
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由 Dan Williams 提交于
Since ioat_cleanup_preamble() and the update of the last completed descriptor are not synchronized there is a chance that two cleanup threads can see descriptors to clean. If the first cleans up all pending descriptors then the second will trigger the BUG_ON. Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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由 Dan Williams 提交于
Replace open coded ioat2_quiesce() call in ioat3_restart_channel Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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由 Dan Williams 提交于
We already disallow raid operations while DCA is globally enabled, so having it locally enabled is a nop and confusing when reading the code. Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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- 20 12月, 2009 1 次提交
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由 Dan Williams 提交于
Put the ioat2 and ioat3 state machines in the halted state with all errors cleared. The ioat1 init path is not disturbed for stability, there are no reported ioat1 initiaization issues. Cc: <stable@kernel.org> Reported-by: NRoland Dreier <rdreier@cisco.com> Tested-by: NRoland Dreier <rdreier@cisco.com> Acked-by: NSimon Horman <horms@verge.net.au> Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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- 18 12月, 2009 1 次提交
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由 Dan Williams 提交于
When continuing a pq calculation the driver needs 3 extra sources. The driver can perform a 3 source calculation with a single descriptor, but needs an extended descriptor to process up to 8 sources in one operation. However, in the p-disabled case only one extra source is needed. When continuing a p-disabled operation there are occasions (i.e. 0 < src_cnt % 8 < 3) where the tail operation does not need an extended descriptor. Properly account for this fact otherwise invalid 'dmacount' values will be written to hardware usually causing the channel to halt with 'invalid descriptor' errors. Cc: <stable@kernel.org> Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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- 20 11月, 2009 5 次提交
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由 Dan Williams 提交于
The completion of a pq operation is notified with a null descriptor appended to the end of the chain. This descriptor needs to be visible to dma clients otherwise the client is precluded from ensuring all operations are quiesced before freeing channel resources, i.e. due to descriptor polling it may get the completion notification ahead of the interrupt delivered by the null descriptor. Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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由 Dan Williams 提交于
ioat3.2 does not support asynchronous error notifications which makes the driver experience latencies when non-zero pq validate results are expected. Provide a mechanism for turning off async_xor_val and async_syndrome_val via Kconfig. This approach is generally useful for any driver that specifies ASYNC_TX_DISABLE_CHANNEL_SWITCH and would like to force the async_tx api to fall back to the synchronous path for certain operations. Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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由 Dan Williams 提交于
Modify is_ioat_bug() to catch all errors that are uncorrectable, or not currently handled. Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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由 Dan Williams 提交于
Although disabled, hardware still checks address validity, so duplicate the known address. Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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由 Dan Williams 提交于
RAID operations cause a system hang on platforms with DCA (Direct-Cache-Access) enabled. So turn off RAID capabilities in this case. Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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- 22 9月, 2009 1 次提交
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由 Dan Williams 提交于
drivers/dma/ioat/dma_v3.c: In function 'ioat3_prep_memset_lock': drivers/dma/ioat/dma_v3.c:439: warning: 'fill' may be used uninitialized in this function drivers/dma/ioat/dma_v3.c:437: warning: 'desc' may be used uninitialized in this function drivers/dma/ioat/dma_v3.c: In function '__ioat3_prep_xor_lock': drivers/dma/ioat/dma_v3.c:489: warning: 'xor' may be used uninitialized in this function drivers/dma/ioat/dma_v3.c:486: warning: 'desc' may be used uninitialized in this function drivers/dma/ioat/dma_v3.c: In function '__ioat3_prep_pq_lock': drivers/dma/ioat/dma_v3.c:631: warning: 'pq' may be used uninitialized in this function drivers/dma/ioat/dma_v3.c:628: warning: 'desc' may be used uninitialized in this function gcc-4.0, unlike gcc-4.3, does not see that these variables are initialized before use. Convert the descriptor loops to do-while make this initialization apparent. Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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- 09 9月, 2009 9 次提交
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由 Dan Williams 提交于
The cleanup routine for the raid cases imposes extra checks for handling raid descriptors and extended descriptors. If the channel does not support raid it can avoid this extra overhead by using the ioat2 cleanup path. Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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由 Dan Williams 提交于
The async_tx api uses the DMA_INTERRUPT operation type to terminate a chain of issued operations with a callback routine. Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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由 Dan Williams 提交于
If a platform advertises pq capabilities, but not xor, then use ioat3_prep_pqxor and ioat3_prep_pqxor_val to simulate xor support. Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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由 Dan Williams 提交于
ioat3.2 adds support for raid6 syndrome generation (xor sum of galois field multiplication products) using up to 8 sources. It can also perform an pq-zero-sum operation to validate whether the syndrome for a given set of sources matches a previously computed syndrome. Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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由 Dan Williams 提交于
This adds a hardware specific self test to be called from ioat_probe. In the ioat3 case we will have tests for all the different raid operations, while ioat1 and ioat2 will continue to just test memcpy. Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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由 Dan Williams 提交于
ioat3.2 adds xor offload support for up to 8 sources. It can also perform an xor-zero-sum operation to validate whether all given sources sum to zero, without writing to a destination. Xor descriptors differ from memcpy in that one operation may require multiple descriptors depending on the number of sources. When the number of sources exceeds 5 an extended descriptor is needed. These descriptors need to be accounted for when updating the DMA_COUNT register. Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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由 Dan Williams 提交于
Tag completion writes for direct cache access to reduce the latency of checking for descriptor completions. Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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由 Dan Williams 提交于
Export driver attributes for diagnostic purposes: 'ring_size': total number of descriptors available to the engine 'ring_active': number of descriptors in-flight 'capabilities': supported operation types for this channel 'version': Intel(R) QuickData specfication revision This also allows some chattiness to be removed from the driver startup as this information is now available via sysfs. Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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由 Dan Williams 提交于
Up until this point the driver for Intel(R) QuickData Technology engines, specification versions 2 and 3, were mostly identical save for a few quirks. Version 3.2 hardware adds many new capabilities (like raid offload support) requiring some infrastructure that is not relevant for v2. For better code organization of the new funcionality move v3 and v3.2 support to its own file dma_v3.c, and export some routines from the base files (dma.c and dma_v2.c) that can be reused directly. The first new capability included in this code reorganization is support for v3.2 memset operations. Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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