1. 24 7月, 2016 2 次提交
    • M
      xtensa: cleanup MMU setup and kernel layout macros · a9f2fc62
      Max Filippov 提交于
      Make kernel load address explicit, independent of the selected MMU
      configuration and configurable from Kconfig. Do not restrict it to the
      first 512MB of the physical address space.
      
      Cleanup kernel memory layout macros:
      
      - rename VECBASE_RESET_VADDR to VECBASE_VADDR, XC_VADDR to VECTOR_VADDR;
      - drop VIRTUAL_MEMORY_ADDRESS and LOAD_MEMORY_ADDRESS;
      - introduce PHYS_OFFSET and use it in __va and __pa definitions;
      - synchronize MMU/noMMU vectors, drop unused NMI vector;
      - replace hardcoded vectors offset of 0x3000 with Kconfig symbol.
      Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
      a9f2fc62
    • M
      xtensa: add alternative kernel memory layouts · d39af902
      Max Filippov 提交于
      MMUv3 is able to support low memory bigger than 128MB.
      Implement 256MB and 512MB KSEG layouts:
      
      - add Kconfig selector for KSEG layout;
      - add KSEG base address, size and alignment definitions to
        arch/xtensa/include/asm/kmem_layout.h;
      - use new definitions in TLB initialization;
      - add build time memory map consistency checks.
      
      See Documentation/xtensa/mmu.txt for the details of new memory layouts.
      Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
      d39af902
  2. 02 11月, 2015 1 次提交
  3. 21 10月, 2014 2 次提交
  4. 15 1月, 2014 2 次提交
  5. 09 5月, 2013 1 次提交
    • M
      xtensa: add MMU v3 support · e85e335f
      Max Filippov 提交于
      MMUv3 comes out of reset with identity vaddr -> paddr mapping in the TLB
      way 6:
      
      Way 6 (512 MB)
              Vaddr       Paddr       ASID  Attr RWX Cache
              ----------  ----------  ----  ---- --- -------
              0x00000000  0x00000000  0x01  0x03 RWX Bypass
              0x20000000  0x20000000  0x01  0x03 RWX Bypass
              0x40000000  0x40000000  0x01  0x03 RWX Bypass
              0x60000000  0x60000000  0x01  0x03 RWX Bypass
              0x80000000  0x80000000  0x01  0x03 RWX Bypass
              0xa0000000  0xa0000000  0x01  0x03 RWX Bypass
              0xc0000000  0xc0000000  0x01  0x03 RWX Bypass
              0xe0000000  0xe0000000  0x01  0x03 RWX Bypass
      
      This patch adds remapping code at the reset vector or at the kernel
      _start (depending on CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX) that
      reconfigures MMUv3 as MMUv2:
      
      Way 5 (128 MB)
              Vaddr       Paddr       ASID  Attr RWX Cache
              ----------  ----------  ----  ---- --- -------
              0xd0000000  0x00000000  0x01  0x07 RWX WB
              0xd8000000  0x00000000  0x01  0x03 RWX Bypass
      Way 6 (256 MB)
              Vaddr       Paddr       ASID  Attr RWX Cache
              ----------  ----------  ----  ---- --- -------
              0xe0000000  0xf0000000  0x01  0x07 RWX WB
              0xf0000000  0xf0000000  0x01  0x03 RWX Bypass
      Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
      Signed-off-by: NChris Zankel <chris@zankel.net>
      e85e335f
  6. 19 12月, 2012 1 次提交