1. 13 2月, 2007 2 次提交
    • A
      [PATCH] x86-64: Allow to run a program when a machine check event is detected · a98f0dd3
      Andi Kleen 提交于
      When a machine check event is detected (including a AMD RevF threshold
      overflow event) allow to run a "trigger" program. This allows user space
      to react to such events sooner.
      
      The trigger is configured using a new trigger entry in the
      machinecheck sysfs interface. It is currently shared between
      all CPUs.
      
      I also fixed the AMD threshold handler to run the machine
      check polling code immediately to actually log any events
      that might have caused the threshold interrupt.
      
      Also added some documentation for the mce sysfs interface.
      Signed-off-by: NAndi Kleen <ak@suse.de>
      a98f0dd3
    • J
      [PATCH] x86-64: Tighten mce_amd driver MSR reads · 24ce0e96
      Jan Beulich 提交于
      while debugging an unrelated problem in Xen, I noticed odd reads from
      non-existent MSRs. Having now found time to look why these happen, I
      came up with below patch, which
      - prevents accessing MCi_MISCj with j > 0 when the block pointer in
      MCi_MISC0 is zero
      - accesses only contiguous MCi_MISCj until a non-implemented one is
      found
      - doesn't touch unimplemented blocks in mce_threshold_interrupt at all
      - gives names to two bits previously derived from MASK_VALID_HI (it
      took me some time to understand the code without this)
      
      The first three items, besides being apparently closer to the spec, should
      namely help cutting down on the time mce_threshold_interrupt() takes.
      Signed-off-by: NAndi Kleen <ak@suse.de>
      24ce0e96
  2. 12 2月, 2007 1 次提交
  3. 08 12月, 2006 1 次提交
  4. 01 8月, 2006 1 次提交
  5. 11 7月, 2006 1 次提交
  6. 27 6月, 2006 5 次提交
  7. 26 4月, 2006 1 次提交
  8. 12 1月, 2006 2 次提交
    • L
      [PATCH] x86_64: Sparse warnings fix. · 68209407
      Luiz Fernando Capitulino 提交于
       Fixes the following sparse warnings:
      
      arch/x86_64/kernel/mce_amd.c:321:29: warning: Using plain integer as NULL pointer
      arch/x86_64/kernel/mce_amd.c:410:41: warning: Using plain integer as NULL pointer
      Signed-off-by: NLuiz Capitulino <lcapitulino@mandriva.com.br>
      Signed-off-by: NAndi Kleen <ak@suse.de>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      68209407
    • A
      [PATCH] x86_64: Add idle notifiers · 95833c83
      Andi Kleen 提交于
      This adds a new notifier chain that is called with IDLE_START
      when a CPU goes idle and IDLE_END when it goes out of idle.
      The context can be idle thread or interrupt context.
      
      Since we cannot rely on MONITOR/MWAIT existing the idle
      end check currently has to be done in all interrupt
      handlers.
      
      They were originally inspired by the similar s390 implementation.
      
      They have a variety of applications:
      - They will be needed for CONFIG_NO_IDLE_HZ
      - They can be used for oprofile to fix up the missing time
      in idle when performance counters don't tick.
      - They can be used for better C state management in ACPI
      - They could be used for microstate accounting.
      
      This is just infrastructure so far, no users.
      Signed-off-by: NAndi Kleen <ak@suse.de>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      95833c83
  9. 15 11月, 2005 1 次提交
    • J
      [PATCH] x86_64: Support for AMD specific MCE Threshold. · 89b831ef
      Jacob Shin 提交于
      MC4_MISC - DRAM Errors Threshold Register realized under AMD K8 Rev F.
      This register is used to count correctable and uncorrectable ECC errors that occur during DRAM read operations.
      The user may interface through sysfs files in order to change the threshold configuration.
      
      bank%d/error_count - reads current error count, write to clear.
      bank%d/interrupt_enable - set/clear interrupt enable.
      bank%d/threshold_limit - read/write the threshold limit.
      
      APIC vector 0xF9 in hw_irq.h.
      5 software defined bank ids in mce.h.
      new apic.c function to setup threshold apic lvt.
      defaults to interrupt off, count enabled, and threshold limit max.
      sysfs interface created on /sys/devices/system/threshold.
      
      AK: added some ifdefs to make it compile on UP
      Signed-off-by: NJacob Shin <jacob.shin@amd.com>
      Signed-off-by: NAndi Kleen <ak@suse.de>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      89b831ef