- 05 3月, 2014 14 次提交
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由 Hans de Goede 提交于
Add nodes for the usb-phy and ehci- and ohci-usb-host controllers. Signed-off-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Hans de Goede 提交于
Add nodes for the usb-phy and ehci- and ohci-usb-host controllers. Signed-off-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Roman Byshko 提交于
Add nodes for the usb-phy and ehci- and ohci-usb-host controllers. Signed-off-by: NRoman Byshko <rbyshko@gmail.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Hans de Goede 提交于
Signed-off-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Hans de Goede 提交于
Add nodes for the usb-phy and ehci- and ohci-usb-host controllers. Signed-off-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Hans de Goede 提交于
Add nodes for the usb-phy and ehci- and ohci-usb-host controllers. Based on fex file settings, the fex file also contains a mysterious line: usb_hub_vcc_en_gpio = port:PB09<1><0><default><0> Which also clashes with usbc0, which has: usb_drv_vbus_gpio = port:PB09<1><0><default><0> So if usb does not work properly we need someone with a hackberry to look closer into this. Signed-off-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Roman Byshko 提交于
Add nodes for the usb-phy and ehci- and ohci-usb-host controllers. Signed-off-by: NRoman Byshko <rbyshko@gmail.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Roman Byshko 提交于
Add nodes for the usb-phy and ehci- and ohci-usb-host controllers. Signed-off-by: NRoman Byshko <rbyshko@gmail.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Roman Byshko 提交于
Add nodes for the usb-phy and ehci- and ohci-usb-host controllers. Signed-off-by: NRoman Byshko <rbyshko@gmail.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Roman Byshko 提交于
Add nodes for the usb-phy and ehci- and ohci-usb-host controllers. Signed-off-by: NRoman Byshko <rbyshko@gmail.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Roman Byshko 提交于
Add nodes for the usb-phy and ehci- and ohci-usb-host controllers. Signed-off-by: NRoman Byshko <rbyshko@gmail.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Hans de Goede 提交于
This patch adds sunxi sata support to A20 boards that have such a connector. Some boards also feature a regulator via a GPIO and support for this is also added. Signed-off-by: NOlliver Schinagl <oliver@schinagl.nl> Signed-off-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Oliver Schinagl 提交于
This patch adds sunxi sata support to A10 boards that have such a connector. Some boards also feature a regulator via a GPIO and support for this is also added. Signed-off-by: NOlliver Schinagl <oliver@schinagl.nl> Signed-off-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Hans de Goede 提交于
Most sunxi boards with a sata connector also have a gpio controlled connector for sata target power and almost all sunxi boards have a gpio controlled vbus for usb1 and usb2. This commit adds an include file for the regulators representing these supplies, avoiding the need to copy and paste the regulator code to allmost all sunxi board dts files. Signed-off-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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- 28 2月, 2014 1 次提交
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由 Maxime Ripard 提交于
The module 0 clock compatibles were changed between the time the patch was sent and it was merged. Update the compatibles. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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- 24 2月, 2014 6 次提交
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由 Maxime Ripard 提交于
The A20-Olinuxino-micro has two SPI bus exposed on its UEXT connectors, enable them. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Maxime Ripard 提交于
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Maxime Ripard 提交于
The A13 has 3 SPI controllers compatible with the one found in the A10. Add them in the DT. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Maxime Ripard 提交于
The A10s has 3 SPI controllers compatible with the one found in the A10. Add them in the DT. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Maxime Ripard 提交于
The A10 has 4 SPI controllers that are now supported. Add them in the DT. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Maxime Ripard 提交于
The A20 has 4 SPI controllers compatible with the one found in the A10. Add them in the DT. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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- 23 2月, 2014 1 次提交
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由 Hans de Goede 提交于
According to Documentation/devicetree/bindings/regulator/regulator.txt regulator nodes should not be placed under 'simple-bus'. Mark Rutland also explains about it at: http://www.spinics.net/lists/linux-usb/msg101497.htmlSigned-off-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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- 18 2月, 2014 5 次提交
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由 Maxime Ripard 提交于
Switch the device tree to the new compatibles introduced in the clock drivers to have a common pattern accross all Allwinner SoCs. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Marc Zyngier 提交于
The Allwinner A20 SoC is built around a pair of Cortex-A7 cores, which have the usual generic timers. Report this in the DT. Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Roman Byshko 提交于
Signed-off-by: NRoman Byshko <rbyshko@gmail.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Roman Byshko 提交于
Signed-off-by: NRoman Byshko <rbyshko@gmail.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Roman Byshko 提交于
Signed-off-by: NRoman Byshko <rbyshko@gmail.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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- 11 2月, 2014 7 次提交
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由 Chen-Yu Tsai 提交于
All Allwinner A20 boards we support can only use either EMAC or GMAC, as they share the same pins. As we have switched all supported to GMAC, we should alias GMAC (the active controller) as ethernet0, so u-boot will insert the MAC address for the correct controller. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Chen-Yu Tsai 提交于
GMAC has better performance and fewer hardware issues. Use the GMAC in MII mode for ethernet instead of the EMAC. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Chen-Yu Tsai 提交于
GMAC has better performance and fewer hardware issues. Use the GMAC in MII mode for ethernet instead of the EMAC. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Chen-Yu Tsai 提交于
The CubieTruck uses the GMAC with an RGMII phy. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Chen-Yu Tsai 提交于
The A20 has EMAC and GMAC muxed on the same pins. Add pin sets with gmac function for MII and RGMII mode to the DTSI. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Chen-Yu Tsai 提交于
Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Chen-Yu Tsai 提交于
The GMAC uses 1 of 2 sources for its transmit clock, depending on the PHY interface mode. Add both sources as dummy clocks, and as parents to the GMAC clock node. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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- 08 2月, 2014 6 次提交
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由 Chen-Yu Tsai 提交于
Device tree naming conventions state that node names should match node function. Change fully functioning clock nodes to match and add clock-output-names to all sunxi clock nodes. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Chen-Yu Tsai 提交于
Device tree naming conventions state that node names should match node function. Change fully functioning clock nodes to match and add clock-output-names to all sunxi clock nodes. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Chen-Yu Tsai 提交于
Device tree naming conventions state that node names should match node function. Change fully functioning clock nodes to match and add clock-output-names to all sunxi clock nodes. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Chen-Yu Tsai 提交于
Device tree naming conventions state that node names should match node function. Change fully functioning clock nodes to match and add clock-output-names to all sunxi clock nodes. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Maxime Ripard 提交于
The A31 has 4 SPI controllers. Add them in the DTSI. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Maxime Ripard 提交于
The module clocks in the A31 are still compatible with the A10 one. Add the SPI module clocks and the PLL6 in the device tree to allow their use by the SPI controllers. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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