The Marvell Armada 38x SoCs contains an RTC which differs from the RTC
used in the other mvebu SoCs until now.  This commit adds the Device Tree
description of this interface at the SoC level.
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Alessandro Zummo <a.zummo@towertech.it>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Arnaud Ebalard <arno@natisbad.org>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Boris BREZILLON <boris.brezillon@free-electrons.com>
Cc: Lior Amsalem <alior@marvell.com>
Cc: Tawfik Bayouk <tawfik@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

In order to update MAC address entries in the ethernet nodes in Device Tree
both mainline U-Boot and Barebox bootloaders accept the same format of aliases,
which is 'ethernetX', where X stands for an interface number.
Other platforms in the mainline Linux, that comprise ethernet references in
'/aliases' node (like various flavours of imx or sunXi), follow the naming
scheme described above.

This commit ajusts ethernet aliases of Marvell Armada 38x SoC to be properly
recognized by bootloaders' MAC address fixup routines.
Signed-off-by: NMarcin Wojtas <mw@semihalf.com>
Reviewed-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: NAndrew Lunn <andrew@lunn.ch>
Link: https://lkml.kernel.org/r/1415980652-7429-5-git-send-email-mw@semihalf.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

The CA9 MPcore SoC Control block is a set of registers that allows to
configure certain internal aspects of the core blocks of the SoC
(Cortex-A9, L2 cache controller, etc.). In most cases, the default
values are fine so they aren't many reasons to touch those registers,
but there is one exception: to support cpuidle on Armada 38x, we need
to modify the value of the CA9 MPcore Reset Control register.

Therefore, this commit adds a new Device Tree binding for this
hardware block, and uses this new binding for the Armada 38x Device
Tree file.
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: devicetree@vger.kernel.org
Link: https://lkml.kernel.org/r/1404913221-17343-11-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

Wildcards in compatible strings should be avoid. "marvell,armada38x"
was recently introduced but was not yet used.

The armada 385 SoC is a superset of the armada 380 SoC (with more CPUs
and more PCIe slots). So this patch replaces the use of
"marvell,armada38x" by the "marvell,armada380" string.
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1403533011-21339-1-git-send-email-gregory.clement@free-electrons.comAcked-by: NAndrew Lunn <andrew@lunn.ch>
Cc: <stable@vger.kernel.org> # v3.15+
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

The Marvell Armada 38x SoCs contains one EHCI controller. This commit
adds the Device Tree description of this interface at the SoC level,
and also enables the USB2 port on the Armada 385 DB platform.
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1400149062-32661-16-git-send-email-gregory.clement@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

The Marvell Armada 38x SoCs contains two xHCI controllers. This commit
adds the Device Tree description of those interfaces at the SoC level,
and also enables the two USB3 ports on the Armada 385 DB platform and
one USB3 port on the Armada 385 RD platform.
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1400149062-32661-15-git-send-email-gregory.clement@free-electrons.comSigned-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

This commit enables the thermal sensor found in Armada 380/385 SoCs.
Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Link: https://lkml.kernel.org/r/1398371004-15807-11-git-send-email-ezequiel.garcia@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

Back when the Armada 370 and Armada XP initial support was introduced,
the only way to pass the clock frequency to the of_serial driver was
through a clock-frequency Device Tree property.

Thanks to 0bbeb3c3 ('of serial port
driver - add clk_get_rate() support'), it is possible to use the
standard 'clocks' DT property to reference the clock used for a
particular UART controller. This clock is then used by the of_serial
driver to retrieve the clock rate.

This commit modifies the SoC-level Device Tree files of Armada 370,
Armada XP, Armada 375 and Armada 38x to use this possibility. Since
there is no gatable clock for the UART controllers, we simply
reference the TCLK, which is the main SoC clock for the peripherals.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1397806908-7550-4-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

The Marvell Armada 38x processors contain two AHCI compatible
interfaces. This commit adds the Device Tree description of those
interfaces at the SoC level, and also enables them on the Armada 385
DB platform, which allows access to both interfaces through SATA
ports.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397574006-5868-4-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

In commit "mmc: sdhci-pxav3: add support for the Armada 38x SDHCI
controller", the sdhci-pxav3 driver has been extended to also be
usable on Armada 38x platforms.

Therefore, this commit adds the necessary Device Tree informations to
declare this SDHCI interface in the Armada 38x SoC, and also in the
Armada 385 Development Board.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: NAndrew Lunn <andrew@lunn.ch>
Link: https://lkml.kernel.org/r/1397486478-16991-2-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

This commit improves the Armada 38x Device Tree to add the CPU reset
and PMSU Device Tree nodes as well as the declaration of the enabling
method for the CPUs. These are needed to get SMP working on Armada 38x
platforms.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483648-26611-12-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

This commit adds the necessary Device Tree information to enable the
coherency fabric on Armada 38x.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483228-25625-11-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

Add the DT nodes to enable the watchdog support available on
Armada 380/385 SoC.
Reviewed-by: NGuenter Roeck <linux@roeck-us.net>
Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Link: https://lkml.kernel.org/r/1397481813-4962-9-git-send-email-ezequiel.garcia@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

The mvmdio driver accesses some register of the Ethernet unit. It
therefore takes a reference and enables a clock. However, on Armada
38x, no clock specification was given in the Device Tree, which leads
the mvmdio driver to fail when being used as a module and loaded
before the mvneta driver: it tries to access a register from a
hardware unit that isn't clocked.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1395790439-21332-3-git-send-email-thomas.petazzoni@free-electrons.comAcked-by: NAndrew Lunn <andrew@lunn.ch>
Acked-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

The Armada 38x SoC family has a NAND controller, compatible
with the controller in Armada 370/375/XP SoCs. Add support for
it in the devicetree file.
Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Link: https://lkml.kernel.org/r/1394742273-5113-5-git-send-email-ezequiel.garcia@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

The Armada 38x SoC family has a clock provider called "Core Divider",
derived from the fixed 2 GHz main PLL clock. This is similar to the
one on A370, A375 and AXP.
Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Link: https://lkml.kernel.org/r/1394742273-5113-4-git-send-email-ezequiel.garcia@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

Armada 38x SoCs have a 2 GHz fixed main PLL that is used to feed
other clocks. This commit adds a DT representation of this clock
through a fixed-clock compatible node.
Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Link: https://lkml.kernel.org/r/1394742273-5113-3-git-send-email-ezequiel.garcia@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

Instead of hardcoding the values of the interrupt flags, use the
macros provided by <include/dt-bindings/interrupt-controller/irq.h>
and <include/dt-bindings/interrupt-controller/arm-gic.h> for the
Armada 375 and Armada 38x Device Tree files.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

Instead of hardcoding 0 and 1 to indicate SPI and PPI GIC interrupts,
use the definitions of <dt-bindings/interrupt-controller/arm-gic.h> to
clarify the Device Tree code.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

The Armada 380 and 385 SoCs are new SoCs from Marvell, based on a
Cortex-A9 cores (single core for 380, dual core for 385) and a number
of hardware blocks that are common with earlier SoCs from the mvebu
family.

The provided Device Tree describes the following parts of the SoC:

 * CPU
 * Device Bus
 * Clocks
 * Interrupt controllers: GIC and MPIC
 * GPIO controllers
 * I2C buses
 * L2 cache
 * MBus controller
 * Pinctrl
 * Serial
 * SPI buses
 * System controller (for reboot)
 * Timer
 * XOR engines
 * PCIe controllers
 * Network interfaces
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

The Armada 375 SoC is a new SoC from Marvell, based on a dual core
Cortex-A9 and a number of hardware blocks that are common with earlier
SoCs from the mvebu family.

The provided Device Tree describes the following parts of the SoC:

 * CPUs
 * Device Bus
 * Clocks
 * Interrupt controllers: GIC and MPIC
 * GPIO controllers
 * I2C buses
 * L2 cache
 * MBus controller
 * SDIO
 * Pinctrl
 * SATA
 * Serial
 * SPI buses
 * System controller (for reboot)
 * Timer
 * XOR engines
 * PCIe controllers
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>