- 29 8月, 2018 2 次提交
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由 Tony Lindgren 提交于
Otherwise we can get the following errors occasionally on some devices: mmc1: tried to HW reset card, got error -110 mmcblk1: error -110 requesting status mmcblk1: recovery failed! print_req_error: I/O error, dev mmcblk1, sector 14329 ... I have one device that hits this error almost on every boot, and another one that hits it only rarely with the other ones I've used behave without problems. I'm not sure if the issue is related to a particular eMMC card model, but in case it is, both of the machines with issues have: # cat /sys/class/mmc_host/mmc1/mmc1:0001/manfid \ /sys/class/mmc_host/mmc1/mmc1:0001/oemid \ /sys/class/mmc_host/mmc1/mmc1:0001/name 0x000045 0x0100 SEM16G and the working ones have: 0x000011 0x0100 016G92 Note that "ti,non-removable" is different as omap_hsmmc_reg_get() does not call omap_hsmmc_disable_boot_regulators() if no_regulator_off_init is set. And currently we set no_regulator_off_init only for "ti,non-removable" and not for "non-removable". It seems that we should have "non-removable" with some other mmc generic property behave in the same way instead of having to use a non-generic property. But let's fix the issue first. Fixes: 7e2f8c0a ("ARM: dts: Add minimal support for motorola droid 4 xt894") Cc: Marcel Partap <mpartap@gmx.net> Cc: Merlijn Wajer <merlijn@wizzup.org> Cc: Michael Scott <hashcode0f@gmail.com> Cc: NeKit <nekit1000@gmail.com> Cc: Pavel Machek <pavel@ucw.cz> Cc: Sebastian Reichel <sre@kernel.org> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Neeraj Dantu 提交于
Fix wrong mode for dts file added by commit bb3e3fbb ("ARM: dts: Add DT support for Octavo Systems OSD3358-SM-RED based on TI AM335x"). Signed-off-by: NNeeraj Dantu <neeraj.dantu@octavosystems.com> CC: Robert Nelson <robertcnelson@gmail.com> CC: Jason Kridner <jkridner@gmail.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 27 8月, 2018 5 次提交
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由 Fabio Estevam 提交于
imx23-evk board has a Seiko 43WVF1G parallel display. Instead of hardcoding the display timings in the device tree, use the "sii,43wvf1g" compatible instead. This aligns with the new mxsfb bindings scheme documented at: Documentation/devicetree/bindings/display/mxsfb.txt Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Fabio Estevam 提交于
It is recommended to place regulators outside simple-bus, so move them accordingly. Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Fabio Estevam 提交于
imx28-evk board has a Seiko 43WVF1G parallel display. Instead of hardcoding the display timings in the device tree, use the "sii,43wvf1g" compatible instead. This aligns with the new mxsfb bindings scheme documented at: Documentation/devicetree/bindings/display/mxsfb.txt Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Fabio Estevam 提交于
It is recommended to place regulators outside simple-bus, so move them accordingly. Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Leonard Crestez 提交于
This reverts commit 1c86c9dd. That commit followed the reference manual but unfortunately the imx7d manual is incorrect. Tested with ath9k pcie card and confirmed internally. Signed-off-by: NLeonard Crestez <leonard.crestez@nxp.com> Acked-by: NLucas Stach <l.stach@pengutronix.de> Fixes: 1c86c9dd ("ARM: dts: imx7d: Invert legacy PCI irq mapping") Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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- 24 8月, 2018 1 次提交
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由 Arnd Bergmann 提交于
Almost all files in the kernel are either plain text or UTF-8 encoded. A couple however are ISO_8859-1, usually just a few characters in a C comments, for historic reasons. This converts them all to UTF-8 for consistency. Link: http://lkml.kernel.org/r/20180724111600.4158975-1-arnd@arndb.deSigned-off-by: NArnd Bergmann <arnd@arndb.de> Acked-by: Simon Horman <horms@verge.net.au> [IPVS portion] Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> [IIO] Acked-by: Michael Ellerman <mpe@ellerman.id.au> [powerpc] Acked-by: NRob Herring <robh@kernel.org> Cc: Joe Perches <joe@perches.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Samuel Ortiz <sameo@linux.intel.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: Rob Herring <robh+dt@kernel.org> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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- 22 8月, 2018 2 次提交
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由 Keerthy 提交于
RTC alarm2 is connected to pmic_en line and hence can be used to control the pmic enabling/disabling. Hence add the system-power-controller for rtc node. Signed-off-by: NKeerthy <j-keerthy@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Pavel Machek 提交于
Vibration GPIOs don't have anything to do with wakeup. Move it to normal section; this fixes vibrations on Droid 4. Fixes: a5effd96 ("ARM: dts: omap4-droid4: Add vibrator") Signed-off-by: NPavel Machek <pavel@ucw.cz> Reviewed-by: NSebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 25 7月, 2018 1 次提交
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由 Benjamin Herrenschmidt 提交于
Add a node for the CVIC (the coprocessor interrupt controller) and add a label to the SRAM node so it can be referenced from the board device-tree file. Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: NJoel Stanley <joel@jms.id.au>
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- 24 7月, 2018 6 次提交
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由 Steven Vanden Branden 提交于
Add mali gpu node to sun4i a10 platforms. Tested with offscreen rendering with lima mesa (freedesktop gitlab) Signed-off-by: NSteven Vanden Branden <stevenvandenbrandenstift@gmail.com> Signed-off-by: NMaxime Ripard <maxime.ripard@bootlin.com>
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由 Simon Shields 提交于
This pin is externally pulled up, so we need to disable the SoC's internal pull down resistor to allow it to function properly. Signed-off-by: NSimon Shields <simon@lineageos.org> Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org>
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由 Simon Shields 提交于
This pin is externally pulled up, so we need to disable the SoC's internal pull-down. Signed-off-by: NSimon Shields <simon@lineageos.org> Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org>
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由 Simon Shields 提交于
This pin is externally pulled up, so we should disable the SoC's pull down resistor in order for the interrupt to function properly. Signed-off-by: NSimon Shields <simon@lineageos.org> Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org>
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由 Simon Shields 提交于
This pins are externally pulled up, and so we should explicitly configure them to disable the SoC-internal pull-downs. Previously we relied on the bootloader doing this in order to allow the buttons to function properly. Signed-off-by: NSimon Shields <simon@lineageos.org> Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org>
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由 Simon Shields 提交于
Currently, we assume that the bootloader has correctly configured the interrupt pin for max77693. This might not actually be the case - so it's better to configure it explicitly. Signed-off-by: NSimon Shields <simon@lineageos.org> Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org>
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- 23 7月, 2018 7 次提交
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由 Geert Uytterhoeven 提交于
Replace the hardcoded clock indices by R8A77470_CLK_* symbols. Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: NBiju Das <biju.das@bp.renesas.com> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Jacopo Mondi 提交于
Add device tree header for GR-Peach's audiocamerashield with MT9V111 image sensor. Signed-off-by: NJacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: NSimon Horman <horms+renesas@verge.net.au> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Michel Pollet 提交于
Add a special enable method for the second CA7 of the R9A06G032 as well as the default value for the "cpu-release-addr" property. Signed-off-by: NMichel Pollet <michel.pollet@bp.renesas.com> Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Michel Pollet 提交于
This adds a base device tree file for the RZN1-DB board, with only the basic support allowing the system to boot to a prompt. Only one UART is used, with only a single CPU running. Signed-off-by: NMichel Pollet <michel.pollet@bp.renesas.com> Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Michel Pollet 提交于
This adds the Renesas R9A06G032 bare bone support. This currently only handles the SYSCTRL block note, generic parts (gic, architected timer) and a UART. Signed-off-by: NMichel Pollet <michel.pollet@bp.renesas.com> Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be> [simon: updated MAINTAINERS file [simon: do not use r9a06g032-sysctrl.h as it is not in the renesas tree yet] Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Wolfram Sang 提交于
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Acked-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Viresh Kumar 提交于
The OPP properties, like "operating-points", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can create an OPP table. Add such missing properties. Fix other missing properties (like, clock latency, voltage tolerance, etc) as well to make it all work. Signed-off-by: NViresh Kumar <viresh.kumar@linaro.org> Reviewed-by: NSimon Horman <horms+renesas@verge.net.au> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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- 22 7月, 2018 5 次提交
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由 Anand Moon 提交于
Add missing GIC interrupts property for pwm nodes. Signed-off-by: NAnand Moon <linux.amoon@gmail.com> Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org>
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由 Viresh Kumar 提交于
The OPP properties, like "operating-points", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can create an OPP table. Add such missing properties. Fix other missing properties (clocks, clock latency) as well to make it all work. Signed-off-by: NViresh Kumar <viresh.kumar@linaro.org> Signed-off-by: NJisheng Zhang <Jisheng.Zhang@synaptics.com> Signed-off-by: NOlof Johansson <olof@lixom.net>
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由 Viresh Kumar 提交于
The OPP properties, like "operating-points", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can create an OPP table. Add such missing properties. Fix other missing property (clock latency) as well to make it all work. Signed-off-by: NViresh Kumar <viresh.kumar@linaro.org> Reviewed-by: NAmit Kucheria <amit.kucheria@linaro.org> Signed-off-by: NAndy Gross <andy.gross@linaro.org>
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由 Bhushan Shah 提交于
The kernel would not boot on the hammerhead hardware due to the following error: mmc0: Timeout waiting for hardware interrupt. mmc0: sdhci: ============ SDHCI REGISTER DUMP =========== mmc0: sdhci: Sys addr: 0x00000200 | Version: 0x00003802 mmc0: sdhci: Blk size: 0x00000200 | Blk cnt: 0x00000200 mmc0: sdhci: Argument: 0x00000000 | Trn mode: 0x00000023 mmc0: sdhci: Present: 0x03e80000 | Host ctl: 0x00000034 mmc0: sdhci: Power: 0x00000001 | Blk gap: 0x00000000 mmc0: sdhci: Wake-up: 0x00000000 | Clock: 0x00000007 mmc0: sdhci: Timeout: 0x0000000e | Int stat: 0x00000000 mmc0: sdhci: Int enab: 0x02ff900b | Sig enab: 0x02ff100b mmc0: sdhci: AC12 err: 0x00000000 | Slot int: 0x00000000 mmc0: sdhci: Caps: 0x642dc8b2 | Caps_1: 0x00008007 mmc0: sdhci: Cmd: 0x00000c1b | Max curr: 0x00000000 mmc0: sdhci: Resp[0]: 0x00000c00 | Resp[1]: 0x00000000 mmc0: sdhci: Resp[2]: 0x00000000 | Resp[3]: 0x00000000 mmc0: sdhci: Host ctl2: 0x00000008 mmc0: sdhci: ADMA Err: 0x00000000 | ADMA Ptr: 0x70040220 mmc0: sdhci: ============================================ mmc0: Card stuck in wrong state! mmcblk0 card_busy_detect status: 0xe00 mmc0: cache flush error -110 mmc0: Reset 0x1 never completed. This patch increases the load on l20 to 0.2 amps for the sdhci and allows the device to boot normally. Signed-off-by: NBhushan Shah <bshah@kde.org> Signed-off-by: NBrian Masney <masneyb@onstation.org> Suggested-by: NBjorn Andersson <bjorn.andersson@linaro.org> Tested-by: NBrian Masney <masneyb@onstation.org> Signed-off-by: NAndy Gross <andy.gross@linaro.org>
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由 Sricharan R 提交于
Fix all nodes to use proper GIC_* macros for the interrupt type and the interrupt trigger settings to avoid the boot warnings. Signed-off-by: NSricharan R <sricharan@codeaurora.org> Tested-by: NAbhishek Sahu <absahu@codeaurora.org> Reviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: NAndy Gross <andy.gross@linaro.org>
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- 21 7月, 2018 7 次提交
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由 Tony Lindgren 提交于
Compared to 4430, 4460 and 4470 just have slightly different l4 cfg ranges. Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Tony Lindgren 提交于
With l4 interconnect hierarchy and ti-sysc interconnect target module data in place, we can simply move all the related child devices to their proper location and enable probing using ti-sysc. In general the first child device address range starts at range 0 from the ti-sysc interconnect target so the move involves adjusting the child device reg properties for that. And we cannot yet move mmu_dsp until we have a proper reset controller driver for rstctrl registers. In case of any regressions, problem devices can be reverted to probe with legacy platform data as needed by moving them back and removing the related interconnect target module node. Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Tony Lindgren 提交于
Before updating wdt2 to probe with ti-sysc we want to have wdt3 probed with ti-sysc to avoid having them unnecessarily swap order. With ti-sysc, we probe child devices at module_init time while and until l4 abe interconnect is converted to use ti-sysc, wdt3 will probe earlier with legacy platform data. Cc: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Tony Lindgren 提交于
Let's add proper interconnect hierarchy for l4 interconnect instances with the related ti-sysc interconnect module data as documented in Documentation/devicetree/bindings/bus/ti-sysc.txt. Using ti-sysc driver binding allows us to start dropping legacy platform data in arch/arm/mach-omap2/omap*hwmod*data.c files later on in favor of ti-sysc dts data. For setting up a proper hierarchy for the interconnect and ti-sysc data, there are multiple reasons: 1. We can use dts ranges to protect registers from being ioremapped from other devices and prevent hard to track issues with failed flush of posted write between modules 2. Some of the ranges may not be accessible to operating systems at all if configured so on high-security devices 3. The interconnect hierarchy provides proper clockdomain hierarchy that can be used for genpd later on 4. We can avoid almost all deferred probe related issues simply by probing the resource providing interconnect instance first for l4 wkup instance 5. With deferred probe issues gone, we can probe everything later at module_init time except for system timer and interrupt controller and their clocks. This data is generated based on platform data from a booted system and the interconnect acces protection registers for ranges. To avoid regressions, we initially validate the device tree provided data against the existing platform data on boot. Each interconnect instance is typically divided into segments to avoid powering up the whole interconnect. And each segment has one or more ranges TI specific interconnect target modules connected to it. Some devices can also have a separate data access port directly to the parent L3 interconnect for DMA that can be set up as a separate range. Note that we cannot yet include this file from omap4.dtsi until child devices are moved to their proper locations in the interconnect hierarchy in the following patch. Otherwise we would have the each module probed twice. Also note that this does not yet add l4 abe instance, that will be added separately later on. Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Anson Huang 提交于
Commit b97872d4 ("ARM: dts: imx: Add missing OPP properties for CPUs") added "operating-points" property for all CPUs, but i.MX7D already has "operating-points-v2" property on both CPUs, so no need to add "operating-points" property again, this patch removes it. Fixes: b97872d4 ("ARM: dts: imx: Add missing OPP properties for CPUs") Signed-off-by: NAnson Huang <Anson.Huang@nxp.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Andrey Smirnov 提交于
Fix a couple of things that were causing warning when building DTB with W=1. Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: cphealy@gmail.com Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: NAndrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Andrey Smirnov 提交于
Add support for the Zodiac Inflight Innovations CFU1 board (VF610-based). Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NAndrey Smirnov <andrew.smirnov@gmail.com> Tested-by: NChris Healy <cphealy@gmail.com> Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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- 20 7月, 2018 4 次提交
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由 Claudiu Beznea 提交于
Fix typo for TD function of pins PIN_PB22 and PIN_PC14 Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: NAlexandre Belloni <alexandre.belloni@bootlin.com>
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由 Ben Whitten 提交于
This adds support for Lairds upcoming SOM module, featuring Marvell WiFi and Bluetooth, 2Gb NAND / 1Gb LPDDR SDRAM, and an Atmel SAMA5D3 CPU. Signed-off-by: NBen Whitten <ben.whitten@lairdtech.com> Signed-off-by: NAlexandre Belloni <alexandre.belloni@bootlin.com>
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由 Ben Whitten 提交于
Add support for the LoRa gateway from Laird, the RG1xx. This board houses the WB50NBT CPU module along with a Semtech SX1301 based concentrator card. https://www.lairdtech.com/products/rg1xx-lora-gatewaySigned-off-by: NBen Whitten <ben.whitten@lairdtech.com> Signed-off-by: NAlexandre Belloni <alexandre.belloni@bootlin.com>
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由 Ben Whitten 提交于
This adds support for Lairds CPU module, featuring Atheros wifi, CSR Bluetooth and, Atmel SAMA5D3 CPU. https://www.lairdtech.com/products/wb50nbt-wi-fi-bluetooth-moduleSigned-off-by: NBen Whitten <ben.whitten@lairdtech.com> Signed-off-by: NAlexandre Belloni <alexandre.belloni@bootlin.com>
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