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  1. 20 4月, 2016 5 次提交
    • T
      PCI: imx6: Add DT property for link gen, default to Gen1 · a5fcec48
      由 Tim Harvey 提交于 
      Freescale has stated [1] that the LVDS clock source of the IMX6 does not
pass the PCI Gen2 clock jitter test, therefore unless an external Gen2
compliant external clock source is present and supplied back to the IMX6
PCIe core via LVDS CLK1/CLK2 you can not claim Gen2 compliance.

Add a DT property to specify Gen1 vs Gen2 and check this before allowing a
Gen2 link.

We default to Gen1 if the property is not present because at this time
there are no IMX6 boards in mainline that 'input' a clock on LVDS
CLK1/CLK2.

In order to be Gen2 compliant on IMX6 you need to:

 - Have a Gen2 compliant external clock generator and route that clock back
   to either LVDS CLK1 or LVDS CLK2 as an input (see IMX6SX-SabreSD
   reference design).

 - Specify this clock in the PCIe node in the DT (i.e.,
   IMX6QDL_CLK_LVDS1_IN or IMX6QDL_CLK_LVDS2_IN instead of
   IMX6QDL_CLK_LVDS1_GATE which configures it as a CLK output).

[1] https://community.freescale.com/message/453209Signed-off-by: NTim Harvey <tharvey@gateworks.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NLucas Stach <l.stach@pengutronix.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
CC: Zhu Richard <Richard.Zhu@freescale.com>
CC: Akshay Bhat <akshay.bhat@timesys.com>
CC: Rob Herring <robh+dt@kernel.org>
CC: Shawn Guo <shawnguo@kernel.org>
      a5fcec48
    • P
      PCI: imx6: Add reset-gpio-active-high boolean property to DT · 3ea8529a
      由 Petr Štetiar 提交于 
      Currently the reset-gpio DT property which controls the PCI bus device
reset signal defaults to active-low reset sequence (L=reset state,
H=operation state) plus the code in reset function isn't GPIO polarity
aware - it doesn't matter if the defined reset-gpio is active-low or
active-high, it will always result into active-low reset sequence.

I've tried to fix it properly and change the reset-gpio reset sequence to
be polarity-aware, but this patch has been accepted and then reverted as it
has introduced few backward incompatible issues:

1. Some DTBs, for example, imx6qdl-sabresd, don't define reset-gpio
polarity correctly:

  reset-gpio = <&gpio7 12 0>;

which means that it's defined as active-high, but in reality it's
active-low; thus it wouldn't work without a DTS fix.

2. The logic in the reset function is inverted:

	gpio_set_value_cansleep(imx6_pcie->reset_gpio, 0)
	msleep(100);
	gpio_set_value_cansleep(imx6_pcie->reset_gpio, 1);

so even if some of the i.MX6 boards had reset-gpio polarity defined
correctly in their DTSes, they would stop working.

As we can't break old DTBs, we can't fix them, so we need to introduce this
new DT reset-gpio-active-high boolean property so we can support boards
with active-high reset sequence.

This active-high reset sequence is for example needed on Apalis SoMs, where
GPIO1_IO28, used to PCIe reset is not connected directly to PERST# PCIe
signal, but it's ORed with RESETBMCU coming off the PMIC, and thus is
inverted, active-high.

Tested-by: Tim Harvey <tharvey@gateworks.com>	# Gateworks Ventana boards (which have active-low PERST#)
Signed-off-by: NPetr Štetiar <ynezz@true.cz>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NLucas Stach <l.stach@pengutronix.de>
Acked-by: NRob Herring <robh@kernel.org>
      3ea8529a
    • P
      ARM: dts: imx6: Fix PCIe reset GPIO polarity on Toradex Apalis Ixora · 4f6926e9
      由 Petr Štetiar 提交于 
      Adding reset-gpio-active-high boolean DT binding property, which we need to
make PCIe working on Apalis SoMs and not break old DTBs. While at it, I've
fixed comment and GPIO polarity.

On Apalis SoMs the GPIO1_IO28 used to PCIe reset is not connected directly
to PERST# PCIe signal, but it's ORed with RESETBMCU coming off the PMIC,
and thus is inverted, active-high.
Signed-off-by: NPetr Štetiar <ynezz@true.cz>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      4f6926e9
    • C
      PCI: imx6: Add initial imx6sx support · e3c06cd0
      由 Christoph Fritz 提交于 
      Add initial PCIe support for the imx6 SoC derivate imx6sx.  PCI MSI support
is untested as the necessary suspend/resume quirk is not included in this
patch.

This patch is heavily based on patches by Richard Zhu.

[bhelgaas: factor out refclk enable, fix adjacent typos in imx6q-pcie.txt]
Signed-off-by: NChristoph Fritz <chf.fritz@googlemail.com>
Acked-by: NRichard Zhu <Richard.Zhu@freescale.com>
Acked-by: NLucas Stach <l.stach@pengutronix.de>
      e3c06cd0
    • B
      PCI: imx6: Factor out ref clock enable · 4d1821e7
      由 Bjorn Helgaas 提交于 
      Factor out ref clock enable to make it cleaner to add imx6sx support.  No
functional change intended.
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Tested-by: NChristoph Fritz <chf.fritz@googlemail.com>
      4d1821e7
  3. 06 4月, 2016 1 次提交
  5. 03 4月, 2016 9 次提交
  7. 02 4月, 2016 25 次提交