Initialize I2C pins on boards with CPM1/CPM2 controllers and document the
i2c bus in booting-without-of.

The boards don't have any I2C chips connected to the I2C bus, so unless
some external chips are connected to the boards, this code is just an
example of setting everything else up.
Signed-off-by: NJochen Friedrich <jochen@scram.de>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Add support for the MPC8536 process and MPC8536DS reference board.  The
MPC8536 is an e500v2 based SoC which eTSEC, USB, SATA, PCI, and PCIe.

The USB and SATA IP blocks are similiar to those on the PQ2 Pro SoCs and
thus use the same drivers.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

It adds the missing RTC node to tqm8548.dts and enables support for
I2C, DS1307 and LM75 in the default configuration.
Signed-off-by: NWolfgang Grandegger <wg@grandegger.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

i8259 PIC is disabled on MPC8610HPCD, and ULi IDE is configured to use
PCI sideband interrupt that is specified in the device tree.

Current HPCD's device tree specify that IDE interrupt is low to high
sensitive, but in practice ULi IDE throws active-high interrupts (not
active-low as all normal PCI devices).
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Rename MPIC label to mpic to match all other 85xx .dts and to fix compile
issue introduced by addition of the DMA node.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Various instances of the EMAC core have varying: 1) number of address
match slots, 2) width of the registers for handling address match slots,
3) number of registers for handling address match slots and 4) base
offset for those registers.

As the driver stands today, it assumes that all EMACs have 4 IAHT and
GAHT 32-bit registers, starting at offset 0x30 from the register base,
with only 16-bits of each used for a total of 64 match slots.

The 405EX(r) and 460EX now use the EMAC4SYNC core rather than the EMAC4
core. This core has 8 IAHT and GAHT registers, starting at offset 0x80
from the register base, with ALL 32-bits of each used for a total of
256 match slots.

This adds a new compatible device tree entry "emac4sync" and a new,
related feature flag "EMAC_FTR_EMAC4SYNC" along with a series of macros
and inlines which supply the appropriate parameterized value based on
the presence or absence of the EMAC4SYNC feature.

The code has further been reworked where appropriate to use those macros
and inlines.

In addition, the register size passed to ioremap is now taken from the
device tree:

	c4 for EMAC4SYNC cores
	74 for EMAC4 cores
	70 for EMAC cores

rather than sizeof (emac_regs).

Finally, the device trees have been updated with the appropriate compatible
entries and resource sizes.

This has been tested on an AMCC Haleakala board such that: 1) inbound
ICMP requests to 'haleakala.local' via MDNS from both Mac OS X 10.4.11
and Ubuntu 8.04 systems as well as 2) outbound ICMP requests from
'haleakala.local' to those same systems in the '.local' domain via MDNS
now work.
Signed-off-by: NGrant Erickson <gerickson@nuovations.com>
Acked-by: NJeff Garzik <jgarzik@pobox.com>
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>

This change to the makefile corrects the build of a simpleImage with initrd.
Signed-off-by: NJohn Linn <john.linn@xilinx>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Since most bootloaders or wrappers tend to update or add some information
to the .dtb they a handled they need some working space to do that in.

By default add 1K of padding via a default setting of DTS_FLAGS.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
Signed-off-by: NPaul Mackerras <paulus@samba.org>

Currently we set the start of the .text section to be 4Mb for pSeries.
In situations where the zImage is > 8Mb we'll fail to boot (due to
overlapping with OF).  Move .text in a zImage from 4MB to 64MB
(well past OF).

We still will not be able to load large zImage unless we also move OF,
to that end, add a note to the zImage ELF to move OF to 32Mb.  If this
is the very first kernel booted then we'll need to move OF manually by
setting real-base.
Signed-off-by: NTony Breeds <tony@bakeyournoodle.com>
Signed-off-by: NPaul Mackerras <paulus@samba.org>

Added DMA nodes for the elo/elo-plus DMA engines.

Renamed the interrupt controller alias in mpc832x_rdb.dts to ipic so that
its the same as all the other boards.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

GCC 4.4.x looks to be adding support for generating out-of-line register
saves/restores based on:

http://gcc.gnu.org/ml/gcc-patches/2008-04/msg01678.html

This breaks the bootwrapper as we'd need to link with libgcc to get the
implementation of the register save/restores.

To workaround this issue, we just stole the save/restore code from gcc
and simplified it down for our needs (integer only).
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
Signed-off-by: NPaul Mackerras <paulus@samba.org>

This makes the sam440ep.dts dts-v1 compliant.
Signed-off-by: NGiuseppe Coviello <gicoviello@gmail.com>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>

The Sam440ep is an high customizable general purpose mini-itx board,
based on the AMCC 440EP and with a LatticeXP FPGA onboard.

It's poduced by ACube Systems Srl (Bassano del Grappa, Italy),
http://www.acube-systems.biz.
Signed-off-by: NGiuseppe Coviello <gicoviello@gmail.com>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>

Add support for the NOR flash found on the AMCC Taishan Board
and enable MTD support in the defconfig.
Signed-off-by: NImre Kaloz <kaloz@openwrt.org>
Acked-by: NStefan Roese <sr@denx.de>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>

This is patch adds board file, device tree, and defconfig for the new
board, made by Freescale Semiconductor Inc. and Logic Product Development.

Currently supported:
1. UEC{1,2,7,4};
2. I2C;
3. SPI;
4. NS16550 serial;
5. PCI and miniPCI;
6. Intel NOR StrataFlash X16 64Mbit PC28F640P30T85;
7. Graphics controller, Fujitsu MB86277.

Not supported in this patch:
1. StMICRO NAND512W3A2BN6E, 512 Mbit (supported with FSL UPM NAND driver);
2. FHCI USB (supported with FHCI driver).
3. QE Serial UCCs (tested to not work with ucc_uart driver, reason
   unknown, yet);
4. ADC AD7843 (tested to work, but support via device tree depends on
   major SPI rework, GPIO API, etc);
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

This patch adds local bus nodes for Flash and CAN to the DTS file
of the TQM8560 module (tqm8560.dts).
Signed-off-by: NWolfgang Grandegger <wg@grandegger.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Some TQM85xx boards could be equipped with up to 1 GiB (NOR) flash
memory and therefore a modified memory map is required and setup by
the board loader. This patch adds an appropriate DTS file.
Signed-off-by: NWolfgang Grandegger <wg@grandegger.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

This patch adds support for the TQM8548 modules from TQ-Components
GmbH (http://www.tqc.de).
Signed-off-by: NWolfgang Grandegger <wg@grandegger.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Like for the TQM5200, the vendor prefix "tqc," is now used for all
TQM85xx modules from TQ-Components GmbH (http://www.tqc.de) in the
corresponding DTS files.
Signed-off-by: NWolfgang Grandegger <wg@grandegger.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

MDIO-less PHYs should use CONFIG_FIXED_PHY driver and appropriate
fixed-link property in the device tree.

If not, ethernet will not work:
  e0024520:03 not found
  eth1: Could not attach to PHY
  IP-Config: Failed to open eth1
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Andrew Klossner pointed out the IO space size was in violation of
the alignment requirements for windows on the 85xx.  The size should
have been 1M (to match u-boot).
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Support for the C2K cPCI Single Board Computer from GEFanuc
(PowerPC MPC7448 with a Marvell MV64460 chipset).
All features of the board are not supported yet, but the board
boots, flash works, all Ethernet ports are working and PCI
devices are all found (USB and SATA on PCI1 do not work yet).

Part 2 of 5: support for the board in arch/powerpc/boot.
Signed-off-by: NRemi Machet <rmachet@slac.stanford.edu>
Signed-off-by: NPaul Mackerras <paulus@samba.org>

Support for the C2K cPCI Single Board Computer from GEFanuc
(PowerPC MPC7448 with a Marvell MV64460 chipset).
All features of the board are not supported yet, but the board
boots, flash works, all Ethernet ports are working and PCI
devices are all found (USB and SATA on PCI1 do not work yet).

Part 1 of 5: DTS file describing the board peripherals.  As far as I
know all peripherals except the FPGA are listed in there (I did not
include the FPGA because a lot of work is needed there).
Signed-off-by: NRemi Machet <rmachet@slac.stanford.edu>
Signed-off-by: NPaul Mackerras <paulus@samba.org>

This corrects the names of two CONFIG_ variables.

Note that the CONFIG_MPC86XADS fix uncovers another bug
(with mpc866_ads_defconfig) that will require fixing:

<--  snip  -->

...
arch/powerpc/boot/dtc -O dtb -o arch/powerpc/boot/mpc866ads.dtb -b 0  /home/bunk/linux/kernel-2.6/git/linux-2.6/arch/powerpc/boot/dts/mpc866ads.dts
DTC: dts->dtb  on file "/home/bunk/linux/kernel-2.6/git/linux-2.6/arch/powerpc/boot/dts/mpc866ads.dts"
  WRAP    arch/powerpc/boot/cuImage.mpc866ads
powerpc64-linux-ld: arch/powerpc/boot/cuboot-mpc866ads.o: No such file: No such file or directory
make[2]: *** [arch/powerpc/boot/cuImage.mpc866ads] Error 1

<--  snip  -->
Reported-by: NRobert P. J. Day <rpjday@crashcourse.ca>
Signed-off-by: NAdrian Bunk <bunk@kernel.org>
Signed-off-by: NPaul Mackerras <paulus@samba.org>

Added next-level-cache to the L1 and a reference to the new L2 label.
This is per the ePAPR 0.94 spec.  Since we are't really dependent on this
today we aren't supporting the "legacy" l2-cache phandle that is specified
in the PPC v2.1 OF Binding spec.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Removed clock-frequency, big-endian, and built-in props as they aren't
specified anywhere.  Also added compatible = "chrp,open-pic" in the
places it was missing.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The following adds support for the Analogue & Micro ASP 8347E, running
Redboot.

http://www.analogue-micro.com/ASP8347.htmlSigned-off-by: NBryan O'Donoghue <bodonoghue@codehermit.ie>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

This patch enabled MSI on 8544ds and 8572ds board.
So far only one MSI interrupt can generate on 8544 board.
Signed-off-by: NJason Jin <Jason.jin@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

This patch enable the MSI on 8610hpcd board.
Through the msi-available-ranges property, All the 256
msi interrupts can be tested on this board.
Signed-off-by: NJason Jin <Jason.jin@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The node for DMA2 in the MPC8610 HPCD device tree has the wrong compatible
properties.  This breaks the DMA driver and the sound driver.
Signed-off-by: NTimur Tabi <timur@freescale.com>
Signed-off-by: NPaul Mackerras <paulus@samba.org>

* Switched from 64M NOR/64M NAND to 4M NOR/256M NAND.
* Full DTM support including critical temperature.
* Added POST information.
* Removed LED function, moved to new LED driver.
* Moved ad7414 to new style I2C initialization.
Signed-off-by: NSean MacLennan <smaclennan@pikatech.com>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>

* Switched from 64M NOR/64M NAND to 4M NOR/256M NAND.
* Added led entries.
* Added fpga-sd entry.
* Added ad7414 entry.
Signed-off-by: NSean MacLennan <smaclennan@pikatech.com>
Acked-by: NGrant Likely <grant.likely@secretlab.ca>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>

This fixes the PCI node in the Rainier to match the spec from AMCC.  A
similar fix was done for 440EPx, which shares the same values as 440GRx.
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>

At the moment we have a mixture of left-over version 0 and new-format
version 1 files in arch/powerpc/boot/dts.  This is potentially
confusing to people new to the dts format attempting to figure it out.

So, this patch converts all the as-yet unconverted dts v0 files and
converts them to v1.  They're mechanically-converted, and not hand
tweaked so in some cases they're not 100% in keeping with usual v1
style, but the convertor program does have some heuristics so the
discrepancies aren't too bad.

I have checked that this patch produces no changes to the resulting
dtb binaries.
Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
Acked-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>
Acked-by: NGeoff Levand <geoffrey.levand@am.sony.com>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>

Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

* Add dtbImage.*
* Added zImage.holly
* Folded zImage.coff.lds into zImage.*lds
* Removed some unused zImage.<foo> ignores
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

dtbImage.* and several zImage. targets get created but never cleaned up.

Also, moved zImage to the clean-files line associated with all other image
results (was previously duplicated).
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The PowerPC 440EP, 440GR, 440EPx, and 440GRx chips have an issue that
causes the PLB3-to-PLB4 bridge to wait indefinitely for transaction
requests that cross the end-of-memory-range boundary.  Since the DDR
controller only returns the valid portion of a read request, the bridge
will prevent other PLB masters from completing their transactions.

This implements the recommended workaround for this errata for chips that
use older versions of firmware that do not already handle it.  The last
4KiB of memory are hidden from the kernel to prevent the problem
transactions from occurring.
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>
Acked-by: NStefan Roese <sr@denx.de>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>

The following adds local bus, flash and MTD partition nodes for
sbc8548. As well, a compatible field for the soc node, so that
of_platform_bus_probe() will pick it up.

Something that is provided through this newly added epld node
is the Hardware Revision which is now being utilized.
Signed-off-by: NJeremy McNicoll <jeremy.mcnicoll@windriver.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Signed-off-by: NZhang Wei <wei.zhang@freescale.com>
Cc: "Nelson, Shannon" <shannon.nelson@intel.com>
Cc: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>