- 08 3月, 2017 14 次提交
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由 Chen-Yu Tsai 提交于
To support multiple display pipelines, we would have multiple crtcs, with one or more planes bound to them. Obviously having hardcoded values for the drm_plane .possible_crtcs field is not going to work. For primary and cursor planes, the value is set by drm_crtc_init_with_planes. We just need to set it for overlay planes. We also fix the value set for the RGB encoder, by referencing the crtc set in sun4i_drv. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Chen-Yu Tsai 提交于
The current layer init code keeps a pointer to the primary plane layer in sun4i_drv. When we eventually support multiple display pipelines, this would force us to keep track of primary planes for all crtcs. And these pointers only get used at bind time. Instead, have the crtc init code iterate through the returned layers to find the primary and cursor layers. And drop the pointer from the sun4i_drv structure. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Chen-Yu Tsai 提交于
The tcon provides part of the functionality of the crtc, and also provides the device node for the output port of the crtc. To be able to use drm_of_find_possible_crtcs(), all crtc must be initialized before any downstream encoders. The other part of the crtc is the display backend. The Rockchip DRM driver does this by first binding all vops, which is their crtc, and this step also creates the crtc objects. Then all remaining hardware components are bound. With the Allwinner display pipeline, we have multiple components comprising the crtc, and varying depths of the display pipeline. Since components are added with a depth first search of the of_graph, we can initialize the crtc object within the tcon bind function. Since the backend precedes the tcon, and the backends cannot be muxed or switched around, we can be sure that the associated backend is already initialized. This patch also moves the crtc pointer from the main drm_device data to the tcon device data. Besides the crtc callbacks, the crtc structure is only used within the tcon driver to signal vblank events from its interrupt handler. As the crtc and layer bits are now called from the tcon bits, we must move them from the sun4i-drm module to the sun4i-tcon module to avoid circular dependencies between the two modules. This is because sun4i-drm also calls into sun4i-tcon. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Chen-Yu Tsai 提交于
This patch moves the sun4i_layers_init call from sun4i_drv_bind to sun4i_crtc_init, and the layers pointer from struct sun4i_drv to struct sun4i_crtc. The layers are bound to a specific crtc, and they are not directly used once initiated. They are used through their included drm_plane structures. Moving the layers into the crtc facilitates binding them to the crtc explicitly, by setting the corresponding bit in their .possible_crtcs fields right after the crtc is initialized. This is done in a later patch. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Chen-Yu Tsai 提交于
The number of defined planes in sun4i_layer is unknown to other parts of the sun4i drm driver. Since the return value of sun4i_layers_init is a list of layers, make it return 1 more empty layer as an end of list guard value. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Chen-Yu Tsai 提交于
The way drm_of_find_possible_crtcs works is it tries to match the remote-endpoint of the given node's various endpoints to all the crtc's .port field. Thus we need to set drm_crtc.port to the output port node of the underlying TCON. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Chen-Yu Tsai 提交于
sunxi_rgb2yuv_coef is a table of RGB-to-YUV conversion coefficients. They are programmed into the hardware, and can be declared constant. Reported-by: NPriit Laes <plaes@plaes.org> Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Chen-Yu Tsai 提交于
sun4i_crtc_init can fail for a number of reasons. Instead of returning a NULL pointer when it fails, pass back the encountered error using ERR_PTR. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Chen-Yu Tsai 提交于
sun4i_layers_init allocates an array to store pointers to newly created layers returned by sun4i_layer_init_one(), but fails to actually store them. But it actually returns the empty array to unsuspecting users. Save the pointers in the array, so that they may be used later. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Chen-Yu Tsai 提交于
The assignment found in the main loop in sun4i_layers_init: struct sun4i_layer *layer = layers[i]; is useless as it gets overwritten by the next line: layer = sun4i_layer_init_one(drm, plane); Drop the assignment. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Chen-Yu Tsai 提交于
In sun4i_layers_init we are allocating an array of pointers to struct sun4i_layer: layers = devm_kcalloc(drm->dev, ARRAY_SIZE(sun4i_backend_planes), sizeof(**layers), GFP_KERNEL); The element size should be the size of an individual element of the array. Change it to sizeof(*layers) to avoid wasting a lot of memory. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Chen-Yu Tsai 提交于
drm_vblank_init can fail due to insufficient memory. Ignoring the error and proceeding may cause the kernel to dereference an invalid pointer when vblank is enabled. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Chen-Yu Tsai 提交于
The master bind function calls numerous drm functions which initialize underlying structures. It also tries to bind the various components of the display pipeline, some of which may add additional drm objects. This patch adds proper cleanup functions in the error path of the master bind function. This requires the patch "drm/sun4i: Move drm_mode_config_cleanup call to main driver", which splits out drm_mode_config_cleanup from sun4i_framebuffer_free so we can call it separately. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Chen-Yu Tsai 提交于
drm_mode_config_cleanup is the complement of drm_mode_config_init, which is called in the bind function of sun4i_drv. drm_mode_config_cleanup should be put in the unbind function to match. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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- 03 3月, 2017 2 次提交
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由 Eric Anholt 提交于
If a CMA allocation failed, the partially constructed BO would be unreferenced through the normal path, and we might choose to put it in the BO cache. If we then reused it before it expired from the cache, the kernel would OOPS. Signed-off-by: NEric Anholt <eric@anholt.net> Fixes: c826a6e1 ("drm/vc4: Add a BO cache.") Reviewed-by: NBoris Brezillon <boris.brezillon@free-electrons.com> Link: http://patchwork.freedesktop.org/patch/msgid/20170301185602.6873-2-eric@anholt.net
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由 Eric Anholt 提交于
The from_cache flag was actually "the BO is invisible to userspace", so we can repurpose it to just zero out a cached BO and return it to userspace. Improves wall time for a loop of 5 glsl-algebraic-add-add-1 by -1.44989% +/- 0.862891% (n=28, 1 outlier removed from each that appeared to be other system noise) Note that there's an intel-gpu-tools test to check for the proper zeroing behavior here, which we continue to pass. Signed-off-by: NEric Anholt <eric@anholt.net> Reviewed-by: NBoris Brezillon <boris.brezillon@free-electrons.com> Link: http://patchwork.freedesktop.org/patch/msgid/20170301185602.6873-1-eric@anholt.net
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- 02 3月, 2017 24 次提交
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由 Daniel Vetter 提交于
This reverts commit 233ce881. I assumed it's ok, but really should have double-checked - CI caught tons of fail :( Cc: Jani Nikula <jani.nikula@intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Acked-by: NManasi Navare <manasi.d.navare@intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20170301171749.13053-1-daniel.vetter@ffwll.ch
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由 Maxime Ripard 提交于
Implement legacy framebuffer ioctl FBIO_WAITFORVSYNC in the generic framebuffer emulation driver. Legacy framebuffer users like non kms/drm based OpenGL(ES)/EGL implementations may require the ioctl to synchronize drawing or buffer flip for double buffering. It is tested on the i.MX6. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Tested-by: NNeil Armstrong <narmstrong@baylibre.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Gabriel Krisman Bertazi 提交于
Commit be7f735cd5ea ("drm: Rely on mode_config data for fb_helper initialization") dropped the num_crtc argument. Update the documentation to reflect that and prevent the kernel-doc warnings below: ./drivers/gpu/drm/drm_fb_cma_helper.c:557: warning: Excess function parameter 'num_crtc' description in 'drm_fbdev_cma_init' ./drivers/gpu/drm/drm_fb_cma_helper.c:558: warning: Excess function parameter 'num_crtc' description in 'drm_fbdev_cma_init' Fixes: be7f735cd5ea ("drm: Rely on mode_config data for fb_helper initialization") Signed-off-by: NGabriel Krisman Bertazi <krisman@collabora.co.uk> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/87o9xkvn2m.fsf@dilma.collabora.co.uk
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由 Chris Zhong 提交于
Reference the power domain incase dw-mipi power down when in use. Signed-off-by: NChris Zhong <zyw@rock-chips.com> Reviewed-by: NSean Paul <seanpaul@chromium.org> Signed-off-by: NSean Paul <seanpaul@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/1487577744-2855-8-git-send-email-zyw@rock-chips.com
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由 Chris Zhong 提交于
Set the lanes bps to 1 / 0.9 times of pclk, the margin is not enough for some panel, it will cause the screen display is not normal, so increases the badnwidth to 1 / 0.8. Signed-off-by: NChris Zhong <zyw@rock-chips.com> Signed-off-by: NSean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/1487577744-2855-7-git-send-email-zyw@rock-chips.com
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由 Chris Zhong 提交于
Signed-off-by: NChris Zhong <zyw@rock-chips.com> Acked-by: NRob Herring <robh@kernel.org> Signed-off-by: NSean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/1487577744-2855-6-git-send-email-zyw@rock-chips.com
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由 Chris Zhong 提交于
The MIPI DSI do not need check the validity of resolution, the max resolution should depend VOP. Hence, remove rk3288_mipi_dsi_mode_valid here. Signed-off-by: NChris Zhong <zyw@rock-chips.com> Signed-off-by: NSean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/1487577744-2855-5-git-send-email-zyw@rock-chips.com
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由 Chris Zhong 提交于
correct the coding style, according the checkpatch scripts Signed-off-by: NChris Zhong <zyw@rock-chips.com> Reviewed-by: NSean Paul <seanpaul@chromium.org> Signed-off-by: NSean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/1487577744-2855-4-git-send-email-zyw@rock-chips.com
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由 Chris Zhong 提交于
The vopb/vopl switch register of RK3399 mipi is different from RK3288, the default setting for mipi dsi mode is different too, so add a of_device_id structure to distinguish them, and make sure set the correct mode before mipi phy init. Signed-off-by: NChris Zhong <zyw@rock-chips.com> Signed-off-by: NMark Yao <mark.yao@rock-chips.com> Reviewed-by: NSean Paul <seanpaul@chromium.org> Signed-off-by: NSean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/1487577744-2855-3-git-send-email-zyw@rock-chips.com
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由 Chris Zhong 提交于
The dw-mipi-dsi of rk3399 is almost the same as rk3288, the rk3399 has additional phy config clock. Signed-off-by: NChris Zhong <zyw@rock-chips.com> Acked-by: NRob Herring <robh@kernel.org> Signed-off-by: NSean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/1487577744-2855-2-git-send-email-zyw@rock-chips.com
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由 John Keeping 提交于
In order to fully reset the state of the MIPI controller we must assert this reset. This is slightly more complicated than it could be in order to maintain compatibility with device trees that do not specify the reset property. Signed-off-by: NJohn Keeping <john@metanate.com> Reviewed-by: NChris Zhong <zyw@rock-chips.com> Signed-off-by: NSean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/20170224125506.21533-24-john@metanate.com
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由 John Keeping 提交于
Signed-off-by: NJohn Keeping <john@metanate.com> Reviewed-by: NChris Zhong <zyw@rock-chips.com> Reviewed-by: NSean Paul <seanpaul@chromium.org> Signed-off-by: NSean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/20170224125506.21533-23-john@metanate.com
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由 John Keeping 提交于
This ensures that the output resolution is known before fbcon loads. mipi_dsi_host_register() is moved above dw_mipi_dsi_register() to simplify error cleanup since the order of these operations does not matter. Signed-off-by: NJohn Keeping <john@metanate.com> Signed-off-by: NSean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/20170224125506.21533-22-john@metanate.com
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由 John Keeping 提交于
When connected to the MIPI DSI output, we need to use N{H,V}SYNC for the internal connection but these flags are meaningless for DSI panels. Switch the test so that we do not set the P{H,V}SYNC bits unless the mode requires it. Signed-off-by: NJohn Keeping <john@metanate.com> Reviewed-by: NMark Yao <mark.yao@rock-chips.com> Reviewed-by: NSean Paul <seanpaul@chromium.org> [seanpaul resolved conflict using macros instead of hardcoded values] Signed-off-by: NSean Paul <seanpaul@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20170224125506.21533-21-john@metanate.com
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由 John Keeping 提交于
This matches other drivers. Signed-off-by: NJohn Keeping <john@metanate.com> Reviewed-by: NSean Paul <seanpaul@chromium.org> Signed-off-by: NSean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/20170224125506.21533-20-john@metanate.com
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由 John Keeping 提交于
As the documentation for readx_poll_timeout says, we want to use the specialized macro for readl rather than using the generic version directly. Signed-off-by: NJohn Keeping <john@metanate.com> Reviewed-by: NChris Zhong <zyw@rock-chips.com> Reviewed-by: NSean Paul <seanpaul@chromium.org> Signed-off-by: NSean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/20170224125506.21533-19-john@metanate.com
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由 John Keeping 提交于
The multiplication ratio for the PLL is required to be even due to the use of a "by 2 pre-scaler". Currently we are likely to end up with an odd multiplier even though there is an equivalent set of parameters with an even multiplier. For example, using the 324MHz bit rate with a reference clock of 24MHz we end up with M = 27, N = 2 whereas the example in the PHY databook gives M = 54, N = 4 for this bit rate and reference clock. By walking down through the available multiplier instead of up we are more likely to hit an even multiplier. With the above example we do now get M = 54, N = 4 as given by the databook. While doing this, change the loop limits to encode the actual limits on the divisor, which are: 40MHz >= (pllref / N) >= 5MHz Signed-off-by: NJohn Keeping <john@metanate.com> Reviewed-by: NSean Paul <seanpaul@chromium.org> Signed-off-by: NSean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/20170224125506.21533-18-john@metanate.com
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由 John Keeping 提交于
These values are specified as constant time periods but the PHY configuration is in terms of the current lane byte clock so using constant values guarantees that the timings will be outside the specification with some display configurations. Derive the necessary configuration from the byte clock in order to ensure that the PHY configuration is correct. Signed-off-by: NJohn Keeping <john@metanate.com> Signed-off-by: NSean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/20170224125506.21533-17-john@metanate.com
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由 John Keeping 提交于
The bias, bandgap and PLL should all be configured before we enable them. Signed-off-by: NJohn Keeping <john@metanate.com> Reviewed-by: NSean Paul <seanpaul@chromium.org> Signed-off-by: NSean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/20170224125506.21533-16-john@metanate.com
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由 John Keeping 提交于
Also don't power up the DSI host at this point since this is not necessary in order to configure the PHY and we do so later when selecting video or command mode. Signed-off-by: NJohn Keeping <john@metanate.com> Reviewed-by: NChris Zhong <zyw@rock-chips.com> Reviewed-by: NSean Paul <seanpaul@chromium.org> Signed-off-by: NSean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/20170224125506.21533-15-john@metanate.com
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由 John Keeping 提交于
This clock rate is derived from the PHY PLL, so it should be calculated dynamically. This calculation is the same as that used by the vendor kernel and ensures that the escape clock runs at <20MHz as required by the MIPI specification. Signed-off-by: NJohn Keeping <john@metanate.com> Reviewed-by: NChris Zhong <zyw@rock-chips.com> Reviewed-by: NSean Paul <seanpaul@chromium.org> Signed-off-by: NSean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/20170224125506.21533-14-john@metanate.com
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由 John Keeping 提交于
Panel drivers may want to sent commands during the disable function, for example MIPI_DCS_SET_DISPLAY_OFF before the video signal ends. In order to send commands we need to write to registers, so pclk must be enabled. While changing this, remove the unnecessary code after the panel unprepare call which seems to be a workaround for a specific panel and thus belongs in the panel driver. Signed-off-by: NJohn Keeping <john@metanate.com> Reviewed-by: NChris Zhong <zyw@rock-chips.com> Reviewed-by: NSean Paul <seanpaul@chromium.org> Signed-off-by: NSean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/20170224125506.21533-13-john@metanate.com
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由 John Keeping 提交于
Some panels need to be configured with commands sent over the MIPI link, which they will do in the prepare hook. Call this after the PHY has been initialized so that we are able to send commands to the panel. Signed-off-by: NJohn Keeping <john@metanate.com> Reviewed-by: NChris Zhong <zyw@rock-chips.com> Reviewed-by: NSean Paul <seanpaul@chromium.org> Signed-off-by: NSean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/20170224125506.21533-12-john@metanate.com
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由 John Keeping 提交于
By dereferencing the MIPI command buffer as a u32* we rely on it being correctly aligned on ARM, but this may not be the case. Copy it into a stack variable that will be correctly aligned. Signed-off-by: NJohn Keeping <john@metanate.com> Reviewed-by: NChris Zhong <zyw@rock-chips.com> Signed-off-by: NSean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/20170224125506.21533-11-john@metanate.com
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