- 17 12月, 2015 10 次提交
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由 Bill Huang 提交于
This fixes two things. - Read the correct IDDQ register - Check the correct IDDQ bit position Signed-off-by: NBill Huang <bilhuang@nvidia.com> Reviewed-by: NBenson Leung <bleung@chromium.org> Signed-off-by: NRhyland Klein <rklein@nvidia.com> Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Andrew Bresticker 提交于
Without this change clk_get_rate would return the final output rather than the VCO output as it would factor in the pdiv when it shouldn't. This will cause problems for all dividers in the subtree of the VCO PLL. Signed-off-by: NAndrew Bresticker <abrestic@chromium.org> Reviewed-by: NBenson Leung <bleung@chromium.org> Signed-off-by: NRhyland Klein <rklein@nvidia.com> Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Rhyland Klein 提交于
Implement clock support for Tegra210. Signed-off-by: NRhyland Klein <rklein@nvidia.com> Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Bill Huang 提交于
Super clock divider control and clock source mux of Tegra210 has changed a little against prior SoCs, this patch adds Gen5 logic to address those differences. Signed-off-by: NBill Huang <bilhuang@nvidia.com> Signed-off-by: NRhyland Klein <rklein@nvidia.com> Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Bill Huang 提交于
Add some logic for Spread Spectrum control. It is used in conjuncture with SDM fractional dividers. SSC has to be disabled when we configure the divider settings. Signed-off-by: NBill Huang <bilhuang@nvidia.com> Signed-off-by: NRhyland Klein <rklein@nvidia.com> Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Rhyland Klein 提交于
Add a callback to the pll_params for custom dynamic ramping functions which can be specified per PLL. Reviewed-by: NBenson Leung <bleung@chromium.org> Signed-off-by: NBill Huang <bilhuang@nvidia.com> Signed-off-by: NRhyland Klein <rklein@nvidia.com> Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Bill Huang 提交于
Add logic which (if specified for a pll) can verify that a PLL is set to the proper default value and if not can set it. This can be specified per PLL as each will have different default values. Based on original work by Aleksandr Frid <afrid@nvidia.com> Signed-off-by: NBill Huang <bilhuang@nvidia.com> Signed-off-by: NRhyland Klein <rklein@nvidia.com> Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Bill Huang 提交于
This code makes use of the SDM fractional divider if present to constrain the allowable programming range of the PLL divider register bitfields to take advantage of higher frequency granularity that can be induced by the SDM divider. Based on original work by Aleksandr Frid <afrid@nvidia.com> Signed-off-by: NBill Huang <bilhuang@nvidia.com> Signed-off-by: NRhyland Klein <rklein@nvidia.com> Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Rhyland Klein 提交于
Tegra210 SoC's have 2 PLLs for memory usage. Add plumbing to register and handle PLLMB. PLLMB is used to allow switching between 2 PLLM's without having to use and intermediate backup PLL, as we need to lock the PLL before we can switch to it. Reviewed-by: NBenson Leung <bleung@chromium.org> Signed-off-by: NRhyland Klein <rklein@nvidia.com> Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Rhyland Klein 提交于
On Tegra210 SoC's, the logic to enable several of the plls is different from previous generations. Therefore, add registration functions specific to Tegra210 which will handle them appropriately. Reviewed-by: NBenson Leung <bleung@chromium.org> Signed-off-by: NRhyland Klein <rklein@nvidia.com> Signed-off-by: NThierry Reding <treding@nvidia.com>
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- 21 11月, 2015 12 次提交
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由 Danny Huang 提交于
PLLM is fixed for Tegra30 up through Tegra114. Starting with Tegra124 PLLM can change rate. Mark PLLM as TEGRA_PLL_FIXED for the generations where it should be. Modify the check in clk_pll_round_rate() and clk_pll_recalc_rate() to allow for the non-fixed version to return the correct rate. Note that there is no change for Tegra20. This is because PLLM is not distinguished in that driver, and adding either the PLLM or FIXED_RATE flags will cause potential problems. PLLM never supported dynamic ramping. On Tegra20 and Tegra30, there is no dynamic ramping at all, and on Tegra114, Tegra124 and Tegra132, only PLLX and PLLC support dynamic ramping, so we can go ahead and remove the specialized pllm_ops. Signed-off-by: NDanny Huang <dahuang@nvidia.com> Signed-off-by: NRhyland Klein <rklein@nvidia.com> Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Rhyland Klein 提交于
This removes the conversion from pdiv to hw, which is already taken care of by _get_table_rate before this code is run. This avoids incorrectly converting pdiv to hw twice and getting the wrong hw value. Also set the input_rate in the freq cfg in _calc_dynamic_ramp_rate while setting all the other fields. In order to prevent regressions on earlier SoC generations, all of the frequency tables need to be updated so that they contain the actual divider values. If they contain hardware values these would be converted to hardware values again, yielding the wrong value. Signed-off-by: NRhyland Klein <rklein@nvidia.com> [treding@nvidia.com: fix regressions on earlier SoC generations] Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Bill Huang 提交于
If a PLL has a reset_reg specified, properly handle that in the enable/disable logic paths. Reviewed-by: NBenson Leung <bleung@chromium.org> Signed-off-by: NBill Huang <bilhuang@nvidia.com> Signed-off-by: NRhyland Klein <rklein@nvidia.com> Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Rhyland Klein 提交于
For Tegra210, the logic to calculate out-of-table rates is different from previous generations. Add callbacks that can be overridden to allow for different ways of calculating rates. Default to _cal_rate when not specified. This patch also includes a new flag which is used to set which method of fixed_mdiv calculation is used. The new method for calculating the fixed divider value for M can be more accurate especially when fractional dividers are in play. This allows for older chipsets to use the existing logic and new generations to use a newer version which may work better for them. Based on original work by Aleksandr Frid <afrid@nvidia.com> Reviewed-by: NBenson Leung <bleung@chromium.org> Signed-off-by: NRhyland Klein <rklein@nvidia.com> Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Rhyland Klein 提交于
This adds logic for taking SDM_DIN (Sigma Delta Modulator) setting into the equation to calculate the effective N value for PLL which supports fractional divider. The effective N = NDIV + 1/2 + SDM_DIN/2^13, where NDIV is the integer feedback divider. Reviewed-by: NBenson Leung <bleung@chromium.org> Signed-off-by: NRhyland Klein <rklein@nvidia.com> Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Rhyland Klein 提交于
SoC specific drivers should define the appropriate flags for each PLL rather than relying on the registration functions to automatically set flags on their behalf. This will properly allow for changes between SoC generations where flags might be different and allow sharing the same logic functions. Reviewed-by: NBenson Leung <bleung@chromium.org> Signed-off-by: NRhyland Klein <rklein@nvidia.com> Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Bill Huang 提交于
New SoC's may have more than 3 MISC registers, so bump up the array size and use a #define to be more informative about the value. Reviewed-by: NBenson Leung <bleung@chromium.org> Signed-off-by: NBill Huang <bilhuang@nvidia.com> Signed-off-by: NRhyland Klein <rklein@nvidia.com> Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Rhyland Klein 提交于
Swap out the generic WARN_ON with a WARN which gives more information about what is happening. Reviewed-by: NBenson Leung <bleung@chromium.org> Signed-off-by: NRhyland Klein <rklein@nvidia.com> Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Rhyland Klein 提交于
Instead of having multiple similar wrapper functions for _clk_pll_[enable|disable], we can simplify it to single wrappers and use checks to avoid the logic we don't want to use. Reviewed-by: NBenson Leung <bleung@chromium.org> Signed-off-by: NRhyland Klein <rklein@nvidia.com> Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Rhyland Klein 提交于
Create a wrapper interface to make use of the existing clk_pll_wait_for_lock. This will be useful for implementations of callbacks in Tegra SoC specific clock drivers. Reviewed-by: NBenson Leung <bleung@chromium.org> Signed-off-by: NRhyland Klein <rklein@nvidia.com> Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Rhyland Klein 提交于
Tegra210 has significant differences in muxes for peripheral clocks. One of the most important changes is that pll_m isn't to be used as a source for peripherals. Therefore, we need to define the new muxes and new clocks to use those muxes for Tegra210 support. Tegra210 has some differences in the PLLP clock tree: - Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO, and PLLP_OUT_XUSB. - PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO. - PLLP_OUT4 is the child of PLLP_OUT_CPU. Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210. Including work by Andrew Bresticker <abrestic@chromium.org> and Bill Huang <bilhuang@nvidia.com>. Signed-off-by: NRhyland Klein <rklein@nvidia.com> Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Thierry Reding 提交于
This is static data that is never modified, so make it const. Signed-off-by: NThierry Reding <treding@nvidia.com>
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- 18 11月, 2015 3 次提交
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由 Thierry Reding 提交于
Use spaces around { and } and pad values so that the cells are properly aligned. Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Thierry Reding 提交于
Use unsigned int for loop variables that can never become negative and remove a couple of gratuitous blank lines. Also use single spaces around operators and use a single space instead of a tab to separate comments from code. Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Thierry Reding 提交于
The OSC_FREQ field of the OSC_CTRL register uses the value 12 for an oscillator frequency of 26 MHz, not 260 MHz. This isn't really critical because I don't think boards with such an oscillator have ever existed, much less been supported upstream. Signed-off-by: NThierry Reding <treding@nvidia.com>
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- 16 11月, 2015 8 次提交
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由 Thierry Reding 提交于
Add a header file that defines the clock numbers for Tegra210. It is meant to be included by device trees so that they can refer to the clocks by symbolic name instead of numeric value. Also add the device tree binding documentation which is largely the same as for earlier generations of Tegra. Extracted from a larger patch by Rhyland Klein <rklein@nvidia.com>. Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Linus Torvalds 提交于
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git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip由 Linus Torvalds 提交于
Pull perf updates from Thomas Gleixner: "Mostly updates to the perf tool plus two fixes to the kernel core code: - Handle tracepoint filters correctly for inherited events (Peter Zijlstra) - Prevent a deadlock in perf_lock_task_context (Paul McKenney) - Add missing newlines to some pr_err() calls (Arnaldo Carvalho de Melo) - Print full source file paths when using 'perf annotate --print-line --full-paths' (Michael Petlan) - Fix 'perf probe -d' when just one out of uprobes and kprobes is enabled (Wang Nan) - Add compiler.h to list.h to fix 'make perf-tar-src-pkg' generated tarballs, i.e. out of tree building (Arnaldo Carvalho de Melo) - Add the llvm-src-base.c and llvm-src-kbuild.c files, generated by the 'perf test' LLVM entries, when running it in-tree, to .gitignore (Yunlong Song) - libbpf error reporting improvements, using a strerror interface to more precisely tell the user about problems with the provided scriptlet, be it in C or as a ready made object file (Wang Nan) - Do not be case sensitive when searching for matching 'perf test' entries (Arnaldo Carvalho de Melo) - Inform the user about objdump failures in 'perf annotate' (Andi Kleen) - Improve the LLVM 'perf test' entry, introduce a new ones for BPF and kbuild tests to check the environment used by clang to compile .c scriptlets (Wang Nan)" * 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (32 commits) perf/x86/intel/rapl: Remove the unused RAPL_EVENT_DESC() macro tools include: Add compiler.h to list.h perf probe: Verify parameters in two functions perf session: Add missing newlines to some pr_err() calls perf annotate: Support full source file paths for srcline fix perf test: Add llvm-src-base.c and llvm-src-kbuild.c to .gitignore perf: Fix inherited events vs. tracepoint filters perf: Disable IRQs across RCU RS CS that acquires scheduler lock perf test: Do not be case sensitive when searching for matching tests perf test: Add 'perf test BPF' perf test: Enhance the LLVM tests: add kbuild test perf test: Enhance the LLVM test: update basic BPF test program perf bpf: Improve BPF related error messages perf tools: Make fetch_kernel_version() publicly available bpf tools: Add new API bpf_object__get_kversion() bpf tools: Improve libbpf error reporting perf probe: Cleanup find_perf_probe_point_from_map to reduce redundancy perf annotate: Inform the user about objdump failures in --stdio perf stat: Make stat options global perf sched latency: Fix thread pid reuse issue ...
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git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip由 Linus Torvalds 提交于
Pull scheduler fix from Thomas Gleixner: "A single fix to prevent math underflow in the numa balancing code" * 'sched-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: sched/numa: Fix math underflow in task_tick_numa()
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git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip由 Linus Torvalds 提交于
Pull liblockdep fixes from Thomas Gleixner: "Three small patches to synchronize liblockdep with the latest core changes" * 'locking-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: tools/liblockdep: explicitly declare lockdep API we call from liblockdep tools/liblockdep: add userspace versions of WRITE_ONCE and RCU_INIT_POINTER tools/liblockdep: remove task argument from debug_check_no_locks_held
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git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip由 Linus Torvalds 提交于
Pull x86 fixes from Thomas Gleixner: "A couple of fixes and updates related to x86: - Fix the W+X check regression on XEN - The real fix for the low identity map trainwreck - Probe legacy PIC early instead of unconditionally allocating legacy irqs - Add cpu verification to long mode entry - Adjust the cache topology to AMD Fam17H systems - Let Merrifield use the TSC across S3" * 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/cpu: Call verify_cpu() after having entered long mode too x86/setup: Fix low identity map for >= 2GB kernel range x86/mm: Skip the hypervisor range when walking PGD x86/AMD: Fix last level cache topology for AMD Fam17h systems x86/irq: Probe for PIC presence before allocating descs for legacy IRQs x86/cpu/intel: Enable X86_FEATURE_NONSTOP_TSC_S3 for Merrifield
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由 Linus Torvalds 提交于
Merge branches 'irq-urgent-for-linus' and 'timers-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull irq and timer fixes from Thomas Gleixner: - An irq regression fix to restore the wakeup behaviour of chained interrupts. - A timer fix for a long standing race versus timers scheduled on a target cpu which got exposed by recent changes in the workqueue implementation. * 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: genirq/PM: Restore system wake up from chained interrupts * 'timers-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: timers: Use proper base migration in add_timer_on()
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git://git.linux-mips.org/pub/scm/ralf/upstream-linus由 Linus Torvalds 提交于
Pull MIPS updates from Ralf Baechle: "These are the highlists of the main MIPS pull request for 4.4: - Add latencytop support - Support appended DTBs - VDSO support and initially use it for gettimeofday. - Drop the .MIPS.abiflags and ELF NOTE sections from vmlinux - Support for the 5KE, an internal test core. - Switch all MIPS platfroms to libata drivers. - Improved support, cleanups for ralink and Lantiq platforms. - Support for the new xilfpga platform. - A number of DTB improvments for BMIPS. - Improved support for CM and CPS. - Minor JZ4740 and BCM47xx enhancements" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (120 commits) MIPS: idle: add case for CPU_5KE MIPS: Octeon: Support APPENDED_DTB MIPS: vmlinux: create a section for appended DTB MIPS: Clean up compat_siginfo_t MIPS: Fix PAGE_MASK definition MIPS: BMIPS: Enable GZIP ramdisk and timed printks MIPS: Add xilfpga defconfig MIPS: xilfpga: Add mipsfpga platform code MIPS: xilfpga: Add xilfpga device tree files. dt-bindings: MIPS: Document xilfpga bindings and boot style MIPS: Make MIPS_CMDLINE_DTB default MIPS: Make the kernel arguments from dtb available MIPS: Use USE_OF as the guard for appended dtb MIPS: BCM63XX: Use pr_* instead of printk MIPS: Loongson: Cleanup CONFIG_LOONGSON_SUSPEND. MIPS: lantiq: Disable xbar fpi burst mode MIPS: lantiq: Force the crossbar to big endian MIPS: lantiq: Initialize the USB core on boot MIPS: lantiq: Return correct value for fpi clock on ar9 MIPS: ralink: Add missing clock on rt305x ...
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- 15 11月, 2015 2 次提交
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git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound由 Linus Torvalds 提交于
Pull sound fixes from Takashi Iwai: "Here are a collection of small fixes tha have been gathered for 4.4-rc1. The only significant changes are those in PCI drivers Kconfig, to use "depends on" instead of "select" for CONFIG_ZONE_DMA. A reverse select is often more user-friendly, but in this case, it makes hard to manage with the conflict with ZONE_DEVICE, so changed in such a way for now. Others are all small fixes and quirks: an error check in soundcore reigster_chrdev(), HD-audio HDMI/DP phantom jack fix, Intel Broxton DP quirk, USB-audio DSD device quirk, some constifications, etc" * tag 'sound-fix-4.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound: ALSA: pci: depend on ZONE_DMA ALSA: hda - Simplify phantom jack handling for HDMI/DP ALSA: hda/hdmi - apply Skylake fix-ups to Broxton display codec ALSA: ctxfi: constify rsc ops structures ALSA: usb: Add native DSD support for Aune X1S ALSA: oxfw: add an comment to Kconfig for TASCAM FireOne sound: fix check for error condition of register_chrdev()
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git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc由 Linus Torvalds 提交于
Pull ARC fixes from Vineet Gupta: "Found a couple of brown paper bag bugs with the prev pull request (including a SMP build breakage report from Guenter). Since these are urgent I also decided to send over a bunch of other pending fixes which could have otherwise waited an rc or two. Summary: - A bunch of brown paper bag bugs (MAINTAINERS list email, SMP build failure) - cpu_relax() now compiler barrier for UP as well - handling of userspace Bus Errors for ARCompact builds" * tag 'arc-4.4-rc1-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: ARC: Fix silly typo in MAINTAINERS file ARC: cpu_relax() to be compiler barrier even for UP ARC: use ASL assembler mnemonic ARC: [arcompact] Handle bus error from userspace as Interrupt not exception ARC: remove extraneous header include ARCv2: lib: memcpy: use local symbols
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- 14 11月, 2015 5 次提交
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由 Vineet Gupta 提交于
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由 Vineet Gupta 提交于
cpu_relax() on ARC has been barrier only for SMP (and no-op for UP). Per recent discussions, it is safer to make it a compiler barrier unconditionally. Link: http://lkml.kernel.org/r/53A7D3AA.9020100@synopsys.comAcked-by: NPeter Zijlstra <peterz@infradead.org> Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
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由 Vineet Gupta 提交于
ARCompact and ARCv2 only have ASL, while binutils used to support LSL as a alias mnemonic. Newer binutils (upstream) don't want to do that so replace it. Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
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由 Vineet Gupta 提交于
Bus errors from userspace on ARCompact based cores are handled by core as a high priority L2 interrupt but current code treated it as interrupt Handling an interrupt like exception is certainly not going to go unnoticed. (and it worked so far as we never saw a Bus error from userspace until IPPK guys tested a DDR controller with ECC error detection etc hence needed to explicitly trigger/handle such errors) - So move mem_service exception handler from common code into ARCv2 code. - In ARCompact code, define mem_service as L2 interrupt handler which just drops down to pure kernel mode and goes of to enqueue SIGBUS Reported-by: NNelson Pereira <npereira@synopsys.com> Tested-by: NAna Martins <amartins@synopsys.com> Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
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由 Vineet Gupta 提交于
Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
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