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  1. 30 12月, 2011 2 次提交
    • S
      sparc32: fix PAGE_SIZE definition · a4b4f437
      由 Sam Ravnborg 提交于 
      Use _AC() in definition of PAGE_SIZE so the same definition
can be used in C and assembler.
Also use PAGE_SIZE in definition of THREAD_SIZE.

This commit kill the following comment:

    "I have my suspicions... -DaveM"

I did not find any clue what this referred to anyway.
Signed-off-by: NSam Ravnborg <sam@ravnborg.org>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      a4b4f437
    • S
      sparc32: enable different preemptions models · b2a1fa30
      由 Sam Ravnborg 提交于 
      While chasing following warning from kconfig I noticed that the
kconfig preemption model symbols were all dependent on sparc64.

warning: (PREEMPT && DEBUG_ATOMIC_SLEEP) selects PREEMPT_COUNT which has unmet direct dependencies (SPARC64)

>From arch/sparc/Kconfig:

        if SPARC64
        source "kernel/Kconfig.preempt"
        endif

But looking a bit closer I see nothing obvious why
sparc32 should not support the various preemption models.
Drop the "if SPARC64" conditional to enable selection of
preemption model on sparc32 too.

Build-tested - but not run-time tested all three models.
Signed-off-by: NSam Ravnborg <sam@ravnborg.org>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      b2a1fa30
  3. 28 12月, 2011 3 次提交
  5. 23 12月, 2011 1 次提交
    • D
      sparc64: Fix MSIQ HV call ordering in pci_sun4v_msiq_build_irq(). · 7cc85833
      由 David S. Miller 提交于 
      This silently was working for many years and stopped working on
Niagara-T3 machines.

We need to set the MSIQ to VALID before we can set it's state to IDLE.

On Niagara-T3, setting the state to IDLE first was causing HV_EINVAL
errors.  The hypervisor documentation says, rather ambiguously, that
the MSIQ must be "initialized" before one can set the state.

I previously understood this to mean merely that a successful setconf()
operation has been performed on the MSIQ, which we have done at this
point.  But it seems to also mean that it has been set VALID too.
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      7cc85833
  7. 15 12月, 2011 1 次提交
  9. 05 12月, 2011 1 次提交
  11. 18 11月, 2011 2 次提交
  13. 16 11月, 2011 1 次提交
    • D
      sparc: Stash orig_i0 into %g6 instead of %g2 · e88d2468
      由 David S. Miller 提交于 
      As per the comments added by this commit, %g2 turns out to not be a
usable place to save away orig_i0 for syscall restart handling.

In fact all of %g2, %g3, %g4, and %g5 are assumed to be saved across
a system call by various bits of code in glibc.

%g1 can't be used because that holds the syscall number, which would
need to be saved and restored for syscall restart handling too, and
that would only compound our problems :-)

This leaves us with %g6 and %g7 which are for "system use".  %g7 is
used as the "thread register" by glibc, but %g6 is used as a compiler
and assembler temporary scratch register.  And in no instance is %g6
used to hold a value across a system call.

Therefore %g6 is safe for storing away orig_i0, at least for now.
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      e88d2468
  15. 15 11月, 2011 1 次提交
    • D
      sparc: Fix handling of orig_i0 wrt. debugging when restarting syscalls. · 1d299bc7
      由 David S. Miller 提交于 
      Although we provide a proper way for a debugger to control whether
syscall restart occurs, we run into problems because orig_i0 is not
saved and restored properly.

Luckily we can solve this problem without having to make debuggers
aware of the issue.  Across system calls, several registers are
considered volatile and can be safely clobbered.

Therefore we use the pt_regs save area of one of those registers, %g2,
as a place to save and restore orig_i0.

Debuggers transparently will do the right thing because they save and
restore this register already.
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      1d299bc7
  17. 14 11月, 2011 1 次提交
  19. 03 11月, 2011 2 次提交
  21. 01 11月, 2011 8 次提交
  23. 31 10月, 2011 1 次提交
  25. 28 10月, 2011 1 次提交
    • E
      compat: sync compat_stats with statfs. · 1448c721
      由 Eric W. Biederman 提交于 
      This was found by inspection while tracking a similar
bug in compat_statfs64, that has been fixed in mainline
since decemeber.

- This fixes a bug where not all of the f_spare fields
  were cleared on mips and s390.
- Add the f_flags field to struct compat_statfs
- Copy f_flags to userspace in case someone cares.
- Use __clear_user to copy the f_spare field to userspace
  to ensure that all of the elements of f_spare are cleared.
  On some architectures f_spare is has 5 ints and on some
  architectures f_spare only has 4 ints.  Which makes
  the previous technique of clearing each int individually
  broken.

I don't expect anyone actually uses the old statfs system
call anymore but if they do let them benefit from having
the compat and the native version working the same.
Signed-off-by: NEric W. Biederman <ebiederm@xmission.com>
Signed-off-by: NChristoph Hellwig <hch@lst.de>
      1448c721
  27. 26 10月, 2011 1 次提交
  29. 21 10月, 2011 3 次提交
  31. 20 10月, 2011 1 次提交
  33. 13 10月, 2011 2 次提交
  35. 08 10月, 2011 1 次提交
  37. 30 9月, 2011 1 次提交
    • D
      sparc64: Force the execute bit in OpenFirmware's translation entries. · f4142cba
      由 David S. Miller 提交于 
      In the OF 'translations' property, the template TTEs in the mappings
never specify the executable bit.  This is the case even though some
of these mappings are for OF's code segment.

Therefore, we need to force the execute bit on in every mapping.

This problem can only really trigger on Niagara/sun4v machines and the
history behind this is a little complicated.

Previous to sun4v, the sun4u TTE entries lacked a hardware execute
permission bit.  So OF didn't have to ever worry about setting
anything to handle executable pages.  Any valid TTE loaded into the
I-TLB would be respected by the chip.

But sun4v Niagara chips have a real hardware enforced executable bit
in their TTEs.  So it has to be set or else the I-TLB throws an
instruction access exception with type code 6 (protection violation).

We've been extremely fortunate to not get bitten by this in the past.

The best I can tell is that the OF's mappings for it's executable code
were mapped using permanent locked mappings on sun4v in the past.
Therefore, the fact that we didn't have the exec bit set in the OF
translations we would use did not matter in practice.

Thanks to Greg Onufer for helping me track this down.
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      f4142cba
  39. 22 9月, 2011 1 次提交
    • D
      sparc: Make '-p' boot option meaningful again. · 11032c17
      由 David S. Miller 提交于 
      If "-p" is given on the command line, clear the CON_BOOT
flag for the initial early boot PROM console.

This is necessary to try and see crash messages that occur
between the registry of the VT console and the probing of
the first framebuffer or serial console.  During this time
no console messages are emitted because the VT console
registry (even if no backend is registered to it) removes
the early console if CON_BOOT is set.
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      11032c17
  41. 21 9月, 2011 1 次提交
  43. 17 9月, 2011 1 次提交
  45. 30 8月, 2011 3 次提交