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  1. 13 4月, 2015 2 次提交
  3. 25 3月, 2015 2 次提交
  5. 19 3月, 2015 3 次提交
    • M
      ARM: socfpga: dts: fix spi1 interrupt · 1ac31de7
      由 Mark James 提交于 
      The socfpga.dtsi currently has the wrong interrupt number set for SPI master 1
Trying to use the master without this change results in the kernel boot
process waiting forever for an interrupt that will never occur while
attempting to probe any slave devices configured in the device tree as being
under SPI master 1.

The change works for the Cyclone V, and according to the Arria 5 handbook
should be good there too.
Signed-off-by: NMark James <maj@jamers.net>
Acked-by: NSteffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>
      1ac31de7
    • T
      ARM: dts: Fix gpio interrupts for dm816x · 599c376c
      由 Tony Lindgren 提交于 
      Commit 7800064b ("ARM: dts: Add basic dm816x device tree
configuration") added basic devices for dm816x, but I was not able
to test the GPIO interrupts earlier until I found some suitable pins
to test with. We can mux the MMC card detect and write protect pins
from SD_SDCD and SD_SDWP mode to use a normal GPIO interrupts that
are also suitable for the MMC subsystem.

This turned out several issues that need to be fixed:

- I set the GPIO type wrong to be compatible with omap3 instead
  of omap4. The GPIO controller on dm816x has EOI interrupt
  register like omap4 and am335x.

- I got the GPIO interrupt numbers wrong as each bank has two
  and we only use one. They need to be set up the same way as
  on am335x.

- The gpio banks are missing interrupt controller related
  properties.

With these changes the GPIO interrupts can be used with the
MMC card detect pin, so let's wire that up. Let's also mux all
the MMC lines for completeness while at it.

For the first GPIO bank I tested using GPMC lines temporarily
muxed to GPIOs on the dip switch 10.

Cc: Brian Hutchinson <b.hutchman@gmail.com>
Cc: Matthijs van Duin <matthijsvanduin@gmail.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>
      599c376c
    • K
      ARM: dts: dra7: remove ti,hwmod property from pcie phy · 07715533
      由 Kishon Vijay Abraham I 提交于 
      Now that we don't have hwmod entry for pcie PHY remove the
ti,hwmod property from PCIE PHY's. Otherwise we will get:

platform 4a094000.pciephy: Cannot lookup hwmod 'pcie1-phy'
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
[tony@atomide.com: updated comments]
Signed-off-by: NTony Lindgren <tony@atomide.com>
      07715533
  7. 18 3月, 2015 5 次提交
  9. 17 3月, 2015 2 次提交
  11. 15 3月, 2015 1 次提交
  13. 12 3月, 2015 1 次提交
    • S
      ARM: imx: fix struct clk pointer comparing · a51139fd
      由 Shawn Guo 提交于 
      Since commit 035a61c3 ("clk: Make clk API return per-user struct clk
instances"), clk API users can no longer check if two struct clk
pointers are pointing to the same hardware clock, i.e. struct clk_hw, by
simply comparing two pointers.  That's because with the per-user clk
change, a brand new struct clk is created whenever clients try to look
up the clock by calling clk_get() or sister functions like clk_get_sys()
and of_clk_get().  This changes the original behavior where the struct
clk is only created for once when clock driver registers the clock to
CCF in the first place.  The net change here is before commit
035a61c3 the struct clk pointer is unique for given hardware
clock, while after the commit the pointers returned by clk lookup calls
become different for the same hardware clock.

That said, the struct clk pointer comparing in the code doesn't work any
more.  Call helper function clk_is_match() instead to fix the problem.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
      a51139fd
  15. 11 3月, 2015 13 次提交
  17. 09 3月, 2015 1 次提交
  19. 07 3月, 2015 10 次提交