1. 07 1月, 2012 1 次提交
  2. 13 7月, 2011 1 次提交
  3. 12 7月, 2011 1 次提交
  4. 08 6月, 2011 3 次提交
  5. 31 3月, 2011 1 次提交
  6. 05 2月, 2011 2 次提交
  7. 06 7月, 2010 1 次提交
  8. 28 8月, 2009 2 次提交
  9. 21 5月, 2009 2 次提交
  10. 19 5月, 2009 1 次提交
  11. 16 12月, 2008 1 次提交
  12. 06 11月, 2008 1 次提交
  13. 05 11月, 2008 1 次提交
    • B
      powerpc/pci: Use common PHB resource hookup · 53280323
      Benjamin Herrenschmidt 提交于
      The 32-bit and 64-bit powerpc PCI code used to set up the resource
      pointers of the root bus of a given PHB in completely different
      places.
      
      This unifies this in large part, by making 32-bit use a routine very
      similar to what 64-bit does when initially scanning the PCI busses.
      
      The actual setup of the PHB resources itself is then moved to a
      common function in pci-common.c.
      
      This should cause no functional change on 64-bit.  On 32-bit, the
      effect is that the PHB resources are going to be setup a bit earlier,
      instead of being setup from pcibios_fixup_bus().
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      53280323
  14. 21 10月, 2008 1 次提交
  15. 04 8月, 2008 1 次提交
  16. 18 6月, 2008 1 次提交
    • J
      powerpc/4xx: Workaround for PPC440EPx/GRx PCI_28 Errata · 5ce4b596
      Josh Boyer 提交于
      The 440EPx/GRx chips don't support PCI MRM commands.  Drivers determine this
      by looking for a zero value in the PCI cache line size register.  However,
      some drivers write to this register upon initialization.  This can cause
      MRMs to be used on these chips, which may cause deadlocks on PLB4.
      
      The workaround implemented here introduces a new indirect_type flag, called
      PPC_INDIRECT_TYPE_BROKEN_MRM.  This is set in the pci_controller structure in
      the pci fixup function for 4xx PCI bridges by determining if the bridge is
      compatible with 440EPx/GRx.  The flag is checked in the indirect_write_config
      function, and forces any writes to the PCI_CACHE_LINE_SIZE register to be
      zero, which will disable MRMs for these chips.
      
      A similar workaround has been tested by AMCC on various PCI cards, such as
      the Silicon Image ATA card and Intel E1000 GIGE card.  Hangs were seen with
      the Silicon Image card, and MRMs were seen on the bus with a PCI analyzer.
      With the workaround in place, the card functioned properly and only Memory
      Reads were seen on the bus with the analyzer.
      Acked-by: NStefan Roese <sr@denx.de>
      Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>
      5ce4b596
  17. 18 4月, 2008 1 次提交
  18. 24 1月, 2008 1 次提交
  19. 17 1月, 2008 3 次提交
  20. 21 12月, 2007 1 次提交
  21. 20 12月, 2007 3 次提交
  22. 11 12月, 2007 4 次提交
  23. 19 11月, 2007 1 次提交
  24. 12 10月, 2007 1 次提交
  25. 26 7月, 2007 1 次提交
  26. 24 7月, 2007 2 次提交
  27. 23 7月, 2007 1 次提交