1. 13 7月, 2007 5 次提交
    • D
      raid5: refactor handle_stripe5 and handle_stripe6 (v3) · a4456856
      Dan Williams 提交于
      handle_stripe5 and handle_stripe6 have very deep logic paths handling the
      various states of a stripe_head.  By introducing the 'stripe_head_state'
      and 'r6_state' objects, large portions of the logic can be moved to
      sub-routines.
      
      'struct stripe_head_state' consumes all of the automatic variables that previously
      stood alone in handle_stripe5,6.  'struct r6_state' contains the handle_stripe6
      specific variables like p_failed and q_failed.
      
      One of the nice side effects of the 'stripe_head_state' change is that it
      allows for further reductions in code duplication between raid5 and raid6.
      The following new routines are shared between raid5 and raid6:
      
      	handle_completed_write_requests
      	handle_requests_to_failed_array
      	handle_stripe_expansion
      
      Changes:
      * v2: fixed 'conf->raid_disk-1' for the raid6 'handle_stripe_expansion' path
      * v3: removed the unused 'dirty' field from struct stripe_head_state
      * v3: coalesced open coded bi_end_io routines into return_io()
      Signed-off-by: NDan Williams <dan.j.williams@intel.com>
      Acked-By: NNeilBrown <neilb@suse.de>
      a4456856
    • D
      async_tx: add the async_tx api · 9bc89cd8
      Dan Williams 提交于
      The async_tx api provides methods for describing a chain of asynchronous
      bulk memory transfers/transforms with support for inter-transactional
      dependencies.  It is implemented as a dmaengine client that smooths over
      the details of different hardware offload engine implementations.  Code
      that is written to the api can optimize for asynchronous operation and the
      api will fit the chain of operations to the available offload resources. 
       
      	I imagine that any piece of ADMA hardware would register with the
      	'async_*' subsystem, and a call to async_X would be routed as
      	appropriate, or be run in-line. - Neil Brown
      
      async_tx exploits the capabilities of struct dma_async_tx_descriptor to
      provide an api of the following general format:
      
      struct dma_async_tx_descriptor *
      async_<operation>(..., struct dma_async_tx_descriptor *depend_tx,
      			dma_async_tx_callback cb_fn, void *cb_param)
      {
      	struct dma_chan *chan = async_tx_find_channel(depend_tx, <operation>);
      	struct dma_device *device = chan ? chan->device : NULL;
      	int int_en = cb_fn ? 1 : 0;
      	struct dma_async_tx_descriptor *tx = device ?
      		device->device_prep_dma_<operation>(chan, len, int_en) : NULL;
      
      	if (tx) { /* run <operation> asynchronously */
      		...
      		tx->tx_set_dest(addr, tx, index);
      		...
      		tx->tx_set_src(addr, tx, index);
      		...
      		async_tx_submit(chan, tx, flags, depend_tx, cb_fn, cb_param);
      	} else { /* run <operation> synchronously */
      		...
      		<operation>
      		...
      		async_tx_sync_epilog(flags, depend_tx, cb_fn, cb_param);
      	}
      
      	return tx;
      }
      
      async_tx_find_channel() returns a capable channel from its pool.  The
      channel pool is organized as a per-cpu array of channel pointers.  The
      async_tx_rebalance() routine is tasked with managing these arrays.  In the
      uniprocessor case async_tx_rebalance() tries to spread responsibility
      evenly over channels of similar capabilities.  For example if there are two
      copy+xor channels, one will handle copy operations and the other will
      handle xor.  In the SMP case async_tx_rebalance() attempts to spread the
      operations evenly over the cpus, e.g. cpu0 gets copy channel0 and xor
      channel0 while cpu1 gets copy channel 1 and xor channel 1.  When a
      dependency is specified async_tx_find_channel defaults to keeping the
      operation on the same channel.  A xor->copy->xor chain will stay on one
      channel if it supports both operation types, otherwise the transaction will
      transition between a copy and a xor resource.
      
      Currently the raid5 implementation in the MD raid456 driver has been
      converted to the async_tx api.  A driver for the offload engines on the
      Intel Xscale series of I/O processors, iop-adma, is provided in a later
      commit.  With the iop-adma driver and async_tx, raid456 is able to offload
      copy, xor, and xor-zero-sum operations to hardware engines.
       
      On iop342 tiobench showed higher throughput for sequential writes (20 - 30%
      improvement) and sequential reads to a degraded array (40 - 55%
      improvement).  For the other cases performance was roughly equal, +/- a few
      percentage points.  On a x86-smp platform the performance of the async_tx
      implementation (in synchronous mode) was also +/- a few percentage points
      of the original implementation.  According to 'top' on iop342 CPU
      utilization drops from ~50% to ~15% during a 'resync' while the speed
      according to /proc/mdstat doubles from ~25 MB/s to ~50 MB/s.
       
      The tiobench command line used for testing was: tiobench --size 2048
      --block 4096 --block 131072 --dir /mnt/raid --numruns 5
      * iop342 had 1GB of memory available
      
      Details:
      * if CONFIG_DMA_ENGINE=n the asynchronous path is compiled away by making
        async_tx_find_channel a static inline routine that always returns NULL
      * when a callback is specified for a given transaction an interrupt will
        fire at operation completion time and the callback will occur in a
        tasklet.  if the the channel does not support interrupts then a live
        polling wait will be performed
      * the api is written as a dmaengine client that requests all available
        channels
      * In support of dependencies the api implicitly schedules channel-switch
        interrupts.  The interrupt triggers the cleanup tasklet which causes
        pending operations to be scheduled on the next channel
      * Xor engines treat an xor destination address differently than a software
        xor routine.  To the software routine the destination address is an implied
        source, whereas engines treat it as a write-only destination.  This patch
        modifies the xor_blocks routine to take a an explicit destination address
        to mirror the hardware.
      
      Changelog:
      * fixed a leftover debug print
      * don't allow callbacks in async_interrupt_cond
      * fixed xor_block changes
      * fixed usage of ASYNC_TX_XOR_DROP_DEST
      * drop dma mapping methods, suggested by Chris Leech
      * printk warning fixups from Andrew Morton
      * don't use inline in C files, Adrian Bunk
      * select the API when MD is enabled
      * BUG_ON xor source counts <= 1
      * implicitly handle hardware concerns like channel switching and
        interrupts, Neil Brown
      * remove the per operation type list, and distribute operation capabilities
        evenly amongst the available channels
      * simplify async_tx_find_channel to optimize the fast path
      * introduce the channel_table_initialized flag to prevent early calls to
        the api
      * reorganize the code to mimic crypto
      * include mm.h as not all archs include it in dma-mapping.h
      * make the Kconfig options non-user visible, Adrian Bunk
      * move async_tx under crypto since it is meant as 'core' functionality, and
        the two may share algorithms in the future
      * move large inline functions into c files
      * checkpatch.pl fixes
      * gpl v2 only correction
      
      Cc: Herbert Xu <herbert@gondor.apana.org.au>
      Signed-off-by: NDan Williams <dan.j.williams@intel.com>
      Acked-By: NNeilBrown <neilb@suse.de>
      9bc89cd8
    • D
      xor: make 'xor_blocks' a library routine for use with async_tx · 685784aa
      Dan Williams 提交于
      The async_tx api tries to use a dma engine for an operation, but will fall
      back to an optimized software routine otherwise.  Xor support is
      implemented using the raid5 xor routines.  For organizational purposes this
      routine is moved to a common area.
      
      The following fixes are also made:
      * rename xor_block => xor_blocks, suggested by Adrian Bunk
      * ensure that xor.o initializes before md.o in the built-in case
      * checkpatch.pl fixes
      * mark calibrate_xor_blocks __init, Adrian Bunk
      
      Cc: Adrian Bunk <bunk@stusta.de>
      Cc: NeilBrown <neilb@suse.de>
      Cc: Herbert Xu <herbert@gondor.apana.org.au>
      Signed-off-by: NDan Williams <dan.j.williams@intel.com>
      685784aa
    • D
      dmaengine: make clients responsible for managing channels · d379b01e
      Dan Williams 提交于
      The current implementation assumes that a channel will only be used by one
      client at a time.  In order to enable channel sharing the dmaengine core is
      changed to a model where clients subscribe to channel-available-events.
      Instead of tracking how many channels a client wants and how many it has
      received the core just broadcasts the available channels and lets the
      clients optionally take a reference.  The core learns about the clients'
      needs at dma_event_callback time.
      
      In support of multiple operation types, clients can specify a capability
      mask to only be notified of channels that satisfy a certain set of
      capabilities.
      
      Changelog:
      * removed DMA_TX_ARRAY_INIT, no longer needed
      * dma_client_chan_free -> dma_chan_release: switch to global reference
        counting only at device unregistration time, before it was also happening
        at client unregistration time
      * clients now return dma_state_client to dmaengine (ack, dup, nak)
      * checkpatch.pl fixes
      * fixup merge with git-ioat
      
      Cc: Chris Leech <christopher.leech@intel.com>
      Signed-off-by: NShannon Nelson <shannon.nelson@intel.com>
      Signed-off-by: NDan Williams <dan.j.williams@intel.com>
      Acked-by: NDavid S. Miller <davem@davemloft.net>
      d379b01e
    • D
      dmaengine: refactor dmaengine around dma_async_tx_descriptor · 7405f74b
      Dan Williams 提交于
      The current dmaengine interface defines mutliple routines per operation,
      i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc.  Adding
      more operation types (xor, crc, etc) to this model would result in an
      unmanageable number of method permutations.
      
      	Are we really going to add a set of hooks for each DMA engine
      	whizbang feature?
      		- Jeff Garzik
      
      The descriptor creation process is refactored using the new common
      dma_async_tx_descriptor structure.  Instead of per driver
      do_<operation>_<dest>_to_<src> methods, drivers integrate
      dma_async_tx_descriptor into their private software descriptor and then
      define a 'prep' routine per operation.  The prep routine allocates a
      descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
      are valid.  Descriptor creation and submission becomes:
      
      struct dma_device *dev;
      struct dma_chan *chan;
      struct dma_async_tx_descriptor *tx;
      
      tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
      tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
      tx->tx_set_dest(dma_addr_t, tx, index)
      tx->tx_submit(tx)
      
      In addition to the refactoring, dma_async_tx_descriptor also lays the
      groundwork for definining cross-channel-operation dependencies, and a
      callback facility for asynchronous notification of operation completion.
      
      Changelog:
      * drop dma mapping methods, suggested by Chris Leech
      * fix ioat_dma_dependency_added, also caught by Andrew Morton
      * fix dma_sync_wait, change from Andrew Morton
      * uninline large functions, change from Andrew Morton
      * add tx->callback = NULL to dmaengine calls to interoperate with async_tx
        calls
      * hookup ioat_tx_submit
      * convert channel capabilities to a 'cpumask_t like' bitmap
      * removed DMA_TX_ARRAY_INIT, no longer needed
      * checkpatch.pl fixes
      * make set_src, set_dest, and tx_submit descriptor specific methods
      * fixup git-ioat merge
      * move group_list and phys to dma_async_tx_descriptor
      
      Cc: Jeff Garzik <jeff@garzik.org>
      Cc: Chris Leech <christopher.leech@intel.com>
      Signed-off-by: NShannon Nelson <shannon.nelson@intel.com>
      Signed-off-by: NDan Williams <dan.j.williams@intel.com>
      Acked-by: NDavid S. Miller <davem@davemloft.net>
      7405f74b
  2. 12 7月, 2007 8 次提交
  3. 09 7月, 2007 4 次提交
  4. 08 7月, 2007 6 次提交
    • B
      qd65xx: fix PIO mode selection · 4660897e
      Bartlomiej Zolnierkiewicz 提交于
      PIO4 is a maximum PIO mode supported by a driver.  Using "255" as a max_mode
      argument to ide_get_best_pio_mode() could result in wrong timings being used
      by a driver (for "pio" equal to 5) or OOPS (for "pio" values > 5 && < 255).
      Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
      Acked-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
      Reviewed-by: NAlan Cox <alan@lxorguk.ukuu.org.uk>
      4660897e
    • U
      sis5513: adding PCI-ID · 4c6c914e
      Uwe Koziolek 提交于
      The SiS966 has one additional PCI-ID 1180.
      
      If the chipset is using this PCI-ID, the primary channel is connected to the
      first PATA-port. The secondary channel is connected to SATA-ports in IDE
      emulation mode.  The legacy IO-ports are used.
      
      The including of the PCI-ID into pata_sis is not sufficient, because the legacy
      driver in drivers/ide is initialized before pata_sis.
      Signed-off-by: NUwe Koziolek <uwe.koziolek@gmx.net>
      Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
      4c6c914e
    • A
      DLM must depend on SYSFS · 95511ad4
      Adrian Bunk 提交于
      The dependency of DLM on SYSFS got lost in
      commit 6ed7257b resulting in the
      following compile error with CONFIG_DLM=y, CONFIG_SYSFS=n:
      
      <--  snip  -->
      
      ...
        LD      .tmp_vmlinux1
      fs/built-in.o: In function `dlm_lockspace_init':
      /home/bunk/linux/kernel-2.6/linux-2.6.22-rc6-mm1/fs/dlm/lockspace.c:231: undefined reference to `kernel_subsys'
      fs/built-in.o: In function `configfs_init':
      /home/bunk/linux/kernel-2.6/linux-2.6.22-rc6-mm1/fs/configfs/mount.c:143: undefined reference to `kernel_subsys'
      make[1]: *** [.tmp_vmlinux1] Error 1
      
      <--  snip  -->
      Signed-off-by: NAdrian Bunk <bunk@stusta.de>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      95511ad4
    • D
      Clean up E7520/7320/7525 quirk printk. · 38377be8
      Dave Jones 提交于
      The printk level in this printk is bogus, as the previous printk
      didn't have a terminating \n resulting in ..
      
      Intel E7520/7320/7525 detected.<6>Disabling irq balancing and affinity
      
      It also never printed a \n at all in the case where we didn't do
      the quirk.
      
      Change it to only make noise if it actually does something useful.
      Signed-off-by: NDave Jones <davej@redhat.com>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      38377be8
    • A
      include/linux/kallsyms.h must #include <linux/errno.h> · 40e48eed
      Adrian Bunk 提交于
      This patch fixes the following 2.6.22 regression with CONFIG_KALLSYMS=n:
      
      <--  snip  -->
      
      ...
        CC      arch/m32r/kernel/traps.o
      In file included from /home/bunk/linux/kernel-2.6/linux-2.6.22-rc6-mm1/arch/m32r/kernel/traps.c:14:
      /home/bunk/linux/kernel-2.6/linux-2.6.22-rc6-mm1/include/linux/kallsyms.h: In function 'lookup_symbol_name':
      /home/bunk/linux/kernel-2.6/linux-2.6.22-rc6-mm1/include/linux/kallsyms.h:66: error: 'ERANGE' undeclared (first use in this function)
      /home/bunk/linux/kernel-2.6/linux-2.6.22-rc6-mm1/include/linux/kallsyms.h:66: error: (Each undeclared identifier is reported only once
      /home/bunk/linux/kernel-2.6/linux-2.6.22-rc6-mm1/include/linux/kallsyms.h:66: error: for each function it appears in.)
      /home/bunk/linux/kernel-2.6/linux-2.6.22-rc6-mm1/include/linux/kallsyms.h: In function 'lookup_symbol_attrs':
      /home/bunk/linux/kernel-2.6/linux-2.6.22-rc6-mm1/include/linux/kallsyms.h:71: error: 'ERANGE' undeclared (first use in this function)
      make[2]: *** [arch/m32r/kernel/traps.o] Error 1
      
      <--  snip  -->
      Signed-off-by: NAdrian Bunk <bunk@stusta.de>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      40e48eed
    • D
      Fix use-after-free oops in Bluetooth HID. · 1c39858b
      David Woodhouse 提交于
      When cleaning up HIDP sessions, we currently close the ACL connection
      before deregistering the input device. Closing the ACL connection
      schedules a workqueue to remove the associated objects from sysfs, but
      the input device still refers to them -- and if the workqueue happens to
      run before the input device removal, the kernel will oops when trying to
      look up PHYSDEVPATH for the removed input device.
      
      Fix this by deregistering the input device before closing the
      connections.
      Signed-off-by: NDavid Woodhouse <dwmw2@infradead.org>
      Acked-by: NMarcel Holtmann <marcel@holtmann.org>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      1c39858b
  5. 07 7月, 2007 14 次提交
  6. 06 7月, 2007 3 次提交
    • R
      [MIPS] Fix scheduling latency issue on 24K, 34K and 74K cores · 4b3e975e
      Ralf Baechle 提交于
      The idle loop goes to sleep using the WAIT instruction if !need_resched().
      This has is suffering from from a race condition that if if just after
      need_resched has returned 0 an interrupt might set TIF_NEED_RESCHED but
      we've just completed the test so go to sleep anyway.  This would be
      trivial to fix by just disabling interrupts during that sequence as in:
      
              local_irq_disable();
              if (!need_resched())
                      __asm__("wait");
              local_irq_enable();
      
      but the processor architecture leaves it undefined if a processor calling
      WAIT with interrupts disabled will ever restart its pipeline and indeed
      some processors have made use of the freedom provided by the architecture
      definition.  This has been resolved and the Config7.WII bit indicates that
      the use of WAIT is safe on 24K, 24KE and 34K cores.  It also is safe on
      74K starting revision 2.1.0 so enable the use of WAIT with interrupts
      disabled for 74K based on a c0_prid of at least that.
      Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      4b3e975e
    • R
      [MIPS] Add macros to encode processor revisions. · fde97822
      Ralf Baechle 提交于
      Older processors used to encode processor version and revision in two
      4-bit bitfields, the 4K seems to simply count up and even newer MTI cores
      have switched to use the 8-bits as 3:3:2 bitfield with the last field as
      the patch number.
      Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      fde97822
    • R
      [MIPS] RM7000: Enable ICACHE_REFILLS_WORKAROUND_WAR. · 075c733e
      Ralf Baechle 提交于
      The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
      opposes it being called that) where invalid instructions in the same
      I-cache line worth of instructions being fetched may case spurious
      exceptions.
      
      The workaround for this was only enabled for E9000 cores; enable it also
      for all RM7000-based platforms.
      Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      075c733e