This patch adds sas and relevant nodes for Hip06 D03 board.

Cc: Xiang Chen <chenxiang66@hisilicon.com>
Cc: John Garry <john.garry@huawei.com>
Signed-off-by: NKefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: NWei Xu <xuwei5@hisilicon.com>

There are four ports(2 GE, 2 XGE) in D03 board, append
relevant nodes for them.

Cc: Kejian Yan <yankejian@huawei.com>
Cc: Yisen Zhuang <yisen.zhuang@huawei.com>
Signed-off-by: NKefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: NWei Xu <xuwei5@hisilicon.com>

The Hip06 soc has same cpu topology compared with Hip05, four clusters
and each cluster has quard Cortex-A57, but with different IO part,
like HNS, SAS and PCI, they are all upgraded. There are also not same
in ITS, MBIGEN and SMMU, etc.

This patch adds the initial dts for hip06 d03 board.

Note, there is no serial, because the soc use LPC uart, the serial node
is not needed.
Signed-off-by: NKefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: NWei Xu <xuwei5@hisilicon.com>