1. 22 11月, 2011 1 次提交
    • D
      viafb: correct sync polarity for OLPC DCON · a3283969
      Daniel Drake 提交于
      While the OLPC display appears to be able to handle either positive
      or negative sync, the Display Controller only recognises positive sync.
      
      This brings viafb (for XO-1.5) in line with lxfb (for XO-1) and
      fixes a recent regression where the XO-1.5 DCON could no longer be
      frozen. Thanks to Florian Tobias Schandinat for helping identify
      the fix.
      
      Test case: from a vt,
      	echo 1 > /sys/devices/platform/dcon/freeze
      should cause the current screen contents to freeze, rather than garbage being
      displayed.
      Signed-off-by: NDaniel Drake <dsd@laptop.org>
      Signed-off-by: NFlorian Tobias Schandinat <FlorianSchandinat@gmx.de>
      Cc: stable@kernel.org
      a3283969
  2. 07 8月, 2011 1 次提交
  3. 05 8月, 2011 1 次提交
  4. 26 4月, 2011 1 次提交
  5. 24 4月, 2011 1 次提交
    • F
      viafb: reduce OLPC refresh a bit · c5a4e6d7
      Florian Tobias Schandinat 提交于
      When allowing some PLL calculation we get a frequency that seems to
      be a bit higher than what the OLPC DCON likes resulting in a still
      readable but not so good image. We don't really know whether this is
      a problem with the calculation formula or the OLPC but as other
      displays seem to be happy with the other modes adjusting the OLPC
      refresh looks like the better thing. This patch prevents a
      regression when dynamic PLL calculation is allowed.
      Signed-off-by: NFlorian Tobias Schandinat <FlorianSchandinat@gmx.de>
      c5a4e6d7
  6. 27 3月, 2011 1 次提交
  7. 12 3月, 2011 2 次提交
  8. 23 7月, 2010 1 次提交
    • F
      viafb: PLL value cleanup · 1f844350
      Florian Tobias Schandinat 提交于
      viafb: PLL value cleanup
      
      This is a big change of how PLL values are handled on the road to
      dynamic PLL value generation. The table was converted automatically in
      the relevant parameters for frequency generation. Sadly there were some
      bits set whose meaning is unknown. Those differences are documented
      but ignored as the unichrome code implies that they are not important
      (a big thanks to Luc for his amazing work).
      The PLL values for 31490000 and 133308000 are deleted as they were more
      than 5% off and not used anyway. The values for CX700@60466000 and
      VX855@153920000 are corrected as they were wrong and easily correctable
      as enough correct values was available because CX700 and VX855 support
      the same values only with a little difference in hardware format.
      All remaining values are not more than 2% off.
      Additionally the surrounding code is changed as needed especially the
      byte order of the values written to hardware to allow nicer conversion
      functions.
      This is mostly a change preparing for dynamic PLL generation and the two
      corrected values aside no runtime change is expected.
      Signed-off-by: NFlorian Tobias Schandinat <FlorianSchandinat@gmx.de>
      Cc: Joseph Chan <JosephChan@via.com.tw>
      1f844350
  9. 12 5月, 2010 1 次提交
  10. 08 5月, 2010 1 次提交
  11. 21 4月, 2010 1 次提交
  12. 13 3月, 2010 2 次提交
  13. 23 9月, 2009 1 次提交
  14. 17 10月, 2008 1 次提交