Rename colibri-pxa270-evalboard to colibri-evalboard as this board is used with
all Colibri modules.
Signed-off-by: NMarek Vasut <marek.vasut@gmail.com>
Acked-by: NDaniel Mack <daniel@caiaq.de>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

Signed-off-by: NMarek Vasut <marek.vasut@gmail.com>
Acked-by: NDaniel Mack <daniel@caiaq.de>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

This change -- pushing the MFP configuration back into Module files -- is
necessary because some evalboards can be used with multiple modules, where MFP
differs from module to module. Therefore MFP isn't board-specific, but
module-specific and the module should preconfigure itself for the board.

(And there is also the C preprocesor limitation and conflicting #define-s)
Signed-off-by: NMarek Vasut <marek.vasut@gmail.com>
Acked-by: NDaniel Mack <daniel@caiaq.de>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

This driver also contains structures to eventually support PXA320. This is
planned to be added in a later patch.
Signed-off-by: NMarek Vasut <marek.vasut@gmail.com>
Acked-by: NDaniel Mack <daniel@caiaq.de>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

On PXA320, there's only one PCMCIA slot available. Check for cases where the
user would want to register multiple. Also, rework failpath.
Signed-off-by: NMarek Vasut <marek.vasut@gmail.com>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

iwmmxt is used in XScale, XScale3, Mohawk and PJ4 core. But the instructions
of accessing CP0 and CP1 is changed in PJ4. Append more files to support
iwmmxt in PJ4 core.
Signed-off-by: NZhou Zhu <zzhu3@marvell.com>
Signed-off-by: NHaojian Zhuang <haojian.zhuang@marvell.com>
Acked-by: NNicolas Pitre <nico@fluxnic.net>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

Signed-off-by: NEric Miao <eric.y.miao@gmail.com>
Signed-off-by: NHaojian Zhuang <haojian.zhuang@marvell.com>

Since CPU_PJ4 is shared between PXA95x and MMP2, select CPU_PJ4 in MMP2
configuration.
Signed-off-by: NHaojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

Saarb platform is a handheld platform that supports Marvell PXA955 silicon.
Signed-off-by: NHaojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

The core of PXA955 is PJ4. Add new PJ4 support. And add new macro
CONFIG_PXA95x.
Signed-off-by: NHaojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

Signed-off-by: NHaojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

Introduce 'struct clk' for memory and remove
get_memclk_frequency_10khz().
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

Define all IRQs in irqs.h. If some IRQs are sharing one IRQ number, define
them together. If some IRQs are sharing same name with different IRQ number,
define different IRQ.
Signed-off-by: NHaojian Zhuang <haojian.zhuang@marvell.com>
Cc: Eric Miao <eric.y.miao@gmail.com>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

After introducing pxa930/pxa935 and new silicons, original cpuid rules
of XScale generation 3 can't fit new silicons. Now redefine the rule
of PXA3xx.

Only PXA300/PXA310/PXA320/PXA930/PXA935 are family members of PXA3xx.
PXA930/PXA935 are family members of PXA93x. PXA93x can be considered
as PXA3xx + CP.
Signed-off-by: NHaojian Zhuang <haojian.zhuang@marvell.com>
Cc: Eric Miao <eric.y.miao@gmail.com>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

Signed-off-by: NHaojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

Signed-off-by: NHaojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

Signed-off-by: NChao Xie <chao.xie@marvell.com>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

Signed-off-by: NDaniel Mack <daniel@caiaq.de>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

This adds a driver for the the 2D graphics accelerator found on PXA3xx
processors. Only resource mapping, interrupt handling and a simple ioctl
handler is done by the kernel part, the rest of the logic is implemented
in DirectFB userspace.

Graphic applications greatly benefit for line drawing, blend, and
rectangle and triangle filling operations.

Benchmarks done on a PXA303 using the df_dok benchmarking tool follow,
where the value in square brackets show the CPU usage during that test.

Without accelerator (benchmarking 256x252 on 480x262 RGB16 (16bit)):

  Anti-aliased Text                              3.016 secs (   65.649 KChars/sec) [ 99.6%]
  Fill Rectangle                                 3.021 secs (  175.107 MPixel/sec) [ 98.0%]
  Fill Rectangle (blend)                         3.582 secs (    3.602 MPixel/sec) [ 99.7%]
  Fill Rectangles [10]                           3.177 secs (  182.753 MPixel/sec) [ 98.1%]
  Fill Rectangles [10] (blend)                  18.020 secs (    3.580 MPixel/sec) [ 98.7%]
  Fill Spans                                     3.019 secs (  145.306 MPixel/sec) [ 98.0%]
  Fill Spans (blend)                             3.616 secs (    3.568 MPixel/sec) [ 99.4%]
  Blit                                           3.074 secs (   39.874 MPixel/sec) [ 98.0%]
  Blit 180                                       3.020 secs (   32.042 MPixel/sec) [ 98.0%]
  Blit with format conversion                    3.005 secs (   19.321 MPixel/sec) [ 99.6%]
  Blit from 32bit (blend)                        4.792 secs (    2.692 MPixel/sec) [ 98.7%]

With accelerator:

  Anti-aliased Text                              3.056 secs (*  36.518 KChars/sec) [ 21.3%]
  Fill Rectangle                                 3.015 secs (* 115.543 MPixel/sec) [  8.9%]
  Fill Rectangle (blend)                         3.180 secs (*  20.286 MPixel/sec) [  1.8%]
  Fill Rectangles [10]                           3.251 secs (* 119.062 MPixel/sec) [  1.2%]
  Fill Rectangles [10] (blend)                   6.293 secs (*  20.502 MPixel/sec) [  0.3%]
  Fill Spans                                     3.051 secs (*  97.264 MPixel/sec) [ 35.7%]
  Fill Spans (blend)                             3.377 secs (*  15.282 MPixel/sec) [ 17.8%]
  Blit                                           3.046 secs (*  27.533 MPixel/sec) [  2.6%]
  Blit 180                                       3.098 secs (*  27.070 MPixel/sec) [  2.2%]
  Blit with format conversion                    3.131 secs (*  39.148 MPixel/sec) [  2.8%]
  Blit from 32bit (blend)                        3.346 secs (*  11.568 MPixel/sec) [  0.8%]
Signed-off-by: NDaniel Mack <daniel@caiaq.de>
Tested-by: NSven Neumann <s.neumann@raumfeld.com>
Cc: Eric Miao <eric.y.miao@gmail.com>
Cc: Denis Oliver Kropp <dok@directfb.org>
Cc: Sven Neumann <s.neumann@raumfeld.com>
Cc: Haojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

Signed-off-by: NZhangfei Gao <zhangfei.gao@marvell.com>
Acked-by: NHaojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

Signed-off-by: NZhangfei Gao <zhangfei.gao@marvell.com>
Acked-by: NHaojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

This is important because on PXA3xx, the physical mapping of SMEMC registers
differs from the one on PXA2xx. In order to get PCMCIA working on both PXA2xx
and PXA320, the PCMCIA driver was adjusted accordingly as well.

Also, various places in the kernel had to be patched to use
__raw_read/__raw_write.
Signed-off-by: NMarek Vasut <marek.vasut@gmail.com>
Acked-by: NHaojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

This patch introduces pxa2xx_map_io() and pxa3xx_map_io() to distinguish
between PXA25x/PXA27x and PXA3xx memory mapping.

Also, fixup for platforms broken after introducing pxa{25x,27x}_map_io()
and pxa3xx_map_io() is included.
Signed-off-by: NMarek Vasut <marek.vasut@gmail.com>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

The camera registers start and range are encoded into the platform
device, and are actually handled by ioremap()'ed, thus the mapping
in pxa_map_io() is not necessary.
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

* git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6:
  crypto: ghash-intel - ghash-clmulni-intel_glue needs err.h

* 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tytso/ext4:
  ext4: fix typo which broke '..' detection in ext4_find_entry()
  ext4: Turn off multiple page-io submission by default

Without this, gcc 4.5 won't compile xen-netfront and xen-blkfront, where
this is being used to specify array sizes.
Signed-off-by: NJan Beulich <jbeulich@novell.com>
Signed-off-by: NJeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com>
Cc: Jens Axboe <axboe@kernel.dk>
Cc: David Miller <davem@davemloft.net>
Cc: Stable Kernel <stable@kernel.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

The MSM main git tree has changed over to this new address.
Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

The install_special_mapping routine (used, for example, to setup the
vdso) skips the security check before insert_vm_struct, allowing a local
attacker to bypass the mmap_min_addr security restriction by limiting
the available pages for special mappings.

bprm_mm_init() also skips the check, and although I don't think this can
be used to bypass any restrictions, I don't see any reason not to have
the security check.

  $ uname -m
  x86_64
  $ cat /proc/sys/vm/mmap_min_addr
  65536
  $ cat install_special_mapping.s
  section .bss
      resb BSS_SIZE
  section .text
      global _start
      _start:
          mov     eax, __NR_pause
          int     0x80
  $ nasm -D__NR_pause=29 -DBSS_SIZE=0xfffed000 -f elf -o install_special_mapping.o install_special_mapping.s
  $ ld -m elf_i386 -Ttext=0x10000 -Tbss=0x11000 -o install_special_mapping install_special_mapping.o
  $ ./install_special_mapping &
  [1] 14303
  $ cat /proc/14303/maps
  0000f000-00010000 r-xp 00000000 00:00 0                                  [vdso]
  00010000-00011000 r-xp 00001000 00:19 2453665                            /home/taviso/install_special_mapping
  00011000-ffffe000 rwxp 00000000 00:00 0                                  [stack]

It's worth noting that Red Hat are shipping with mmap_min_addr set to
4096.
Signed-off-by: NTavis Ormandy <taviso@google.com>
Acked-by: NKees Cook <kees@ubuntu.com>
Acked-by: NRobert Swiecki <swiecki@google.com>
[ Changed to not drop the error code - akpm ]
Reviewed-by: NJames Morris <jmorris@namei.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

Add missing header file:

arch/x86/crypto/ghash-clmulni-intel_glue.c:256: error: implicit declaration of function 'IS_ERR'
arch/x86/crypto/ghash-clmulni-intel_glue.c:257: error: implicit declaration of function 'PTR_ERR'
Signed-off-by: NRandy Dunlap <randy.dunlap@oracle.com>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/wq:
  workqueue: It is likely that WORKER_NOT_RUNNING is true
  MAINTAINERS: Add workqueue entry
  workqueue: check the allocation of system_unbound_wq

* 'for-linus' of git://neil.brown.name/md:
  md: protect against NULL reference when waiting to start a raid10.
  md: fix bug with re-adding of partially recovered device.
  md: fix possible deadlock in handling flush requests.
  md: move code in to submit_flushes.
  md: remove handling of flush_pending in md_submit_flush_data

There is a possibility that the last word of a transaction will be lost
if data is not ready.  Re-read in poll_transfer() to solve this issue
when poll_mode is enabled.

Verified on SPI touch screen device.
Signed-off-by: NMajor Lee <major_lee@wistron.com>
Signed-off-by: NAlan Cox <alan@linux.intel.com>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

This gets caught by the new sanity check code. Instead of the slash use a
different symbol. This was originally found by Major Lee who proposed a
rather more complex patch which changed the name according to the chip
type.

On the basis that we are in a late -rc and making Linus grumpy isn't always
a good idea (however fun) this is a simple alternative.
Signed-off-by: NAlan Cox <alan@linux.intel.com>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

There should be a check for the NUL character instead of '0'.

Fortunately the only thing that cares about this is NFS serving, which
is why we didn't notice this in the merge window testing.
Reported-by: NPhil Carmody <ext-phil.2.carmody@nokia.com>
Signed-off-by: NAaro Koskinen <aaro.koskinen@nokia.com>
Signed-off-by: N"Theodore Ts'o" <tytso@mit.edu>