1. 29 1月, 2009 23 次提交
  2. 21 1月, 2009 1 次提交
    • T
      x86: make x86_32 use tlb_64.c · 02cf94c3
      Tejun Heo 提交于
      Impact: less contention when issuing invalidate IPI, cleanup
      
      Make x86_32 use the same tlb code as 64bit.  The 64bit code uses
      multiple IPI vectors for tlb shootdown to reduce contention.  This
      patch makes x86_32 allocate the same 8 IPIs as x86_64 and share the
      code paths.
      
      Note that the usage of asmlinkage is inconsistent for x86_32 and 64
      and calls for further cleanup.  This has been noted with a FIXME
      comment in tlb_64.c.
      Signed-off-by: NTejun Heo <tj@kernel.org>
      02cf94c3
  3. 13 1月, 2009 1 次提交
  4. 04 1月, 2009 1 次提交
  5. 18 12月, 2008 1 次提交
    • M
      x86: fix cpu_mask_to_apicid_and to include cpu_online_mask · a775a38b
      Mike Travis 提交于
      Impact: fix potential APIC crash
      
      In determining the destination apicid, there are usually three cpumasks
      that are considered: the incoming cpumask arg, cfg->domain and the
      cpu_online_mask.  Since we are just introducing the cpu_mask_to_apicid_and
      function, make sure it includes the cpu_online_mask in it's evaluation.
      [Added with this patch.]
      
      There are two io_apic.c functions that did not previously use the
      cpu_online_mask:  setup_IO_APIC_irq and msi_compose_msg.  Both of these
      simply used cpu_mask_to_apicid(cfg->domain & TARGET_CPUS), and all but
      one arch (NUMAQ[*]) returns only online cpus in the TARGET_CPUS mask,
      so the behavior is identical for all cases.
      
      [*: NUMAQ bug?]
      
      Note that alloc_cpumask_var is only used for the 32-bit cases where
      it's highly likely that the cpumask set size will be small and therefore
      CPUMASK_OFFSTACK=n.  But if that's not the case, failing the allocate
      will cause the same return value as the default.
      Signed-off-by: NMike Travis <travis@sgi.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      a775a38b
  6. 17 12月, 2008 4 次提交
  7. 18 11月, 2008 2 次提交
    • Y
      x86: fix wakeup_cpu with numaq/es7000, v2, fix · 54ac14a8
      Yinghai Lu 提交于
      Impact: fix wakeup_secondary_cpu with hotplug
      
      We can not put that into x86_quirks, because that is __initdata.
      So try to move that to genapic, and add update_genapic in x86_quirks.
      
      later we even could use that stub to:
      
       1. autodetect CONFIG_ES7000_CLUSTERED_APIC
       2. more correct inquire_remote_apic with apic_verbosity setting.
      Signed-off-by: NYinghai Lu <yinghai@kernel.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      54ac14a8
    • Y
      x86: fix wakeup_cpu with numaq/es7000, v2 · 569712b2
      Yinghai Lu 提交于
      Impact: fix secondary-CPU wakeup/init path with numaq and es7000
      
      While looking at wakeup_secondary_cpu for WAKE_SECONDARY_VIA_NMI:
      
      |#ifdef WAKE_SECONDARY_VIA_NMI
      |/*
      | * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
      | * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
      | * won't ... remember to clear down the APIC, etc later.
      | */
      |static int __devinit
      |wakeup_secondary_cpu(int logical_apicid, unsigned long start_eip)
      |{
      |        unsigned long send_status, accept_status = 0;
      |        int maxlvt;
      |...
      |        if (APIC_INTEGRATED(apic_version[phys_apicid])) {
      |                maxlvt = lapic_get_maxlvt();
      
      I noticed that there is no warning about undefined phys_apicid...
      
      because WAKE_SECONDARY_VIA_NMI and WAKE_SECONDARY_VIA_INIT can not be
      defined at the same time. So NUMAQ is using wrong wakeup_secondary_cpu.
      
      WAKE_SECONDARY_VIA_NMI, WAKE_SECONDARY_VIA_INIT and
      WAKE_SECONDARY_VIA_MIP are variants of a weird and fragile
      preprocessor-driven "HAL" mechanisms to specify the kind of secondary-CPU
      wakeup strategy a given x86 kernel will use.
      
      The vast majority of systems want to use INIT for secondary wakeup - NUMAQ
      uses an NMI, (old-style-) ES7000 uses 'MIP' (a firmware driven in-memory
      flag to let secondaries continue).
      
      So convert these mechanisms to x86_quirks and add a
      ->wakeup_secondary_cpu() method to specify the rare exception
      to the sane default.
      
      Extend genapic accordingly as well, for 32-bit.
      
      While looking further, I noticed that functions in wakecup.h for numaq
      and es7000 are different to the default in mach_wakecpu.h - but smpboot.c
      will only use default mach_wakecpu.h with smphook.h.
      
      So we need to add mach_wakecpu.h for mach_generic, to properly support
      numaq and es7000, and vectorize the following SMP init methods:
      
      	int trampoline_phys_low;
      	int trampoline_phys_high;
      	void (*wait_for_init_deassert)(atomic_t *deassert);
      	void (*smp_callin_clear_local_apic)(void);
      	void (*store_NMI_vector)(unsigned short *high, unsigned short *low);
      	void (*restore_NMI_vector)(unsigned short *high, unsigned short *low);
      	void (*inquire_remote_apic)(int apicid);
      Signed-off-by: NYinghai Lu <yinghai@kernel.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      569712b2
  8. 28 10月, 2008 1 次提交
  9. 23 10月, 2008 3 次提交