1. 25 10月, 2016 1 次提交
  2. 20 10月, 2016 7 次提交
  3. 19 10月, 2016 22 次提交
  4. 18 10月, 2016 10 次提交
    • L
      Merge branch 'core-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip · 351267d9
      Linus Torvalds 提交于
      Pull misc fixes from Ingo Molnar:
       "A CPU hotplug debuggability fix and three objtool false positive
        warnings fixes for new GCC6 code generation patterns"
      
      * 'core-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
        cpu/hotplug: Use distinct name for cpu_hotplug.dep_map
        objtool: Skip all "unreachable instruction" warnings for gcov kernels
        objtool: Improve rare switch jump table pattern detection
        objtool: Support '-mtune=atom' stack frame setup instruction
      351267d9
    • L
      Merge tag 'firewire-update' of git://git.kernel.org/pub/scm/linux/kernel/git/ieee1394/linux1394 · 5aa43efe
      Linus Torvalds 提交于
      Pull firewire fixlet from Stefan Richter:
       "IEEE 1394 subsystem patch: catch an initialization error in the packet
        sniffer nosy"
      
      * tag 'firewire-update' of git://git.kernel.org/pub/scm/linux/kernel/git/ieee1394/linux1394:
        firewire: nosy: do not ignore errors in ioremap_nocache()
      5aa43efe
    • L
      Merge tag 'drm-fixes-for-v4.9-rc2' of git://people.freedesktop.org/~airlied/linux · 37c1e289
      Linus Torvalds 提交于
      Pull drm fixes from Dave Airlie:
       "Just had a couple of amdgpu fixes and one core fix I wanted to get out
        early to fix some regressions.
      
        I'm sure I'll have more stuff this week for -rc2"
      
      * tag 'drm-fixes-for-v4.9-rc2' of git://people.freedesktop.org/~airlied/linux: (22 commits)
        drm: Print device information again in debugfs
        drm/amd/powerplay: fix bug stop dpm can't work on Vi.
        drm/amd/powerplay: notify smu no display by default.
        drm/amdgpu/dpm: implement thermal sensor for CZ/ST
        drm/amdgpu/powerplay: implement thermal sensor for CZ/ST
        drm/amdgpu: disable smu hw first on tear down
        drm/amdgpu: fix amdgpu_need_full_reset (v2)
        drm/amdgpu/si_dpm: Limit clocks on HD86xx part
        drm/amd/powerplay: fix static checker warnings in smu7_hwmgr.c
        drm/amdgpu: potential NULL dereference in debugfs code
        drm/amd/powerplay: fix static checker warnings in smu7_hwmgr.c
        drm/amd/powerplay: fix static checker warnings in iceland_smc.c
        drm/radeon: change vblank_time's calculation method to reduce computational error.
        drm/amdgpu: change vblank_time's calculation method to reduce computational error.
        drm/amdgpu: clarify UVD/VCE special handling for CG
        drm/amd/amdgpu: enable clockgating only after late init
        drm/radeon: allow TA_CS_BC_BASE_ADDR on SI
        drm/amdgpu: initialize the context reset_counter in amdgpu_ctx_init
        drm/amdgpu/gfx8: fix CGCG_CGLS handling
        drm/radeon: fix modeset tear down code
        ...
      37c1e289
    • M
      pinctrl: intel: Only restore pins that are used by the driver · c538b943
      Mika Westerberg 提交于
      Dell XPS 13 (and maybe some others) uses a GPIO (CPU_GP_1) during suspend
      to explicitly disable USB touchscreen interrupt. This is done to prevent
      situation where the lid is closed the touchscreen is left functional.
      
      The pinctrl driver (wrongly) assumes it owns all pins which are owned by
      host and not locked down. It is perfectly fine for BIOS to use those pins
      as it is also considered as host in this context.
      
      What happens is that when the lid of Dell XPS 13 is closed, the BIOS
      configures CPU_GP_1 low disabling the touchscreen interrupt. During resume
      we restore all host owned pins to the known state which includes CPU_GP_1
      and this overwrites what the BIOS has programmed there causing the
      touchscreen to fail as no interrupts are reaching the CPU anymore.
      
      Fix this by restoring only those pins we know are explicitly requested by
      the kernel one way or other.
      
      Cc: stable@vger.kernel.org
      Link: https://bugzilla.kernel.org/show_bug.cgi?id=176361Reported-by: NAceLan Kao <acelan.kao@canonical.com>
      Tested-by: NAceLan Kao <acelan.kao@canonical.com>
      Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      c538b943
    • V
      pinctrl: baytrail: Fix lockdep · a171bc51
      Ville Syrjälä 提交于
      Initialize the spinlock before using it.
      
      INFO: trying to register non-static key.
      the code is fine but needs lockdep annotation.
      turning off the locking correctness validator.
      CPU: 2 PID: 1 Comm: swapper/0 Not tainted 4.8.0-dwc-bisect #4
      Hardware name: Intel Corp. VALLEYVIEW C0 PLATFORM/BYT-T FFD8, BIOS BLAKFF81.X64.0088.R10.1403240443 FFD8_X64_R_2014_13_1_00 03/24/2014
       0000000000000000 ffff8800788ff770 ffffffff8133d597 0000000000000000
       0000000000000000 ffff8800788ff7e0 ffffffff810cfb9e 0000000000000002
       ffff8800788ff7d0 ffffffff8205b600 0000000000000002 ffff8800788ff7f0
      Call Trace:
       [<ffffffff8133d597>] dump_stack+0x67/0x90
       [<ffffffff810cfb9e>] register_lock_class+0x52e/0x540
       [<ffffffff810d2081>] __lock_acquire+0x81/0x16b0
       [<ffffffff810cede1>] ? save_trace+0x41/0xd0
       [<ffffffff810d33b2>] ? __lock_acquire+0x13b2/0x16b0
       [<ffffffff810cf05a>] ? __lock_is_held+0x4a/0x70
       [<ffffffff810d3b1a>] lock_acquire+0xba/0x220
       [<ffffffff8136f1fe>] ? byt_gpio_get_direction+0x3e/0x80
       [<ffffffff81631567>] _raw_spin_lock_irqsave+0x47/0x60
       [<ffffffff8136f1fe>] ? byt_gpio_get_direction+0x3e/0x80
       [<ffffffff8136f1fe>] byt_gpio_get_direction+0x3e/0x80
       [<ffffffff813740a9>] gpiochip_add_data+0x319/0x7d0
       [<ffffffff81631723>] ? _raw_spin_unlock_irqrestore+0x43/0x70
       [<ffffffff8136fe3b>] byt_pinctrl_probe+0x2fb/0x620
       [<ffffffff8142fb0c>] platform_drv_probe+0x3c/0xa0
      ...
      
      Based on the diff it looks like the problem was introduced in
      commit 71e6ca61 ("pinctrl: baytrail: Register pin control handling")
      but I wasn't able to verify that empirically as the parent commit
      just oopsed when I tried to boot it.
      
      Cc: Cristina Ciocan <cristina.ciocan@intel.com>
      Cc: stable@vger.kernel.org
      Fixes: 71e6ca61 ("pinctrl: baytrail: Register pin control handling")
      Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Acked-by: NMika Westerberg <mika.westerberg@linux.intel.com>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      a171bc51
    • A
      pinctrl: aspeed-g5: Fix pin association of SPI1 function · 8eb37aff
      Andrew Jeffery 提交于
      The SPI1 function was associated with the wrong pins: The functions that
      those pins provide is either an SPI debug or passthrough function
      coupled to SPI1. Make the SPI1 mux function configure the relevant pins
      and associate new SPI1DEBUG and SPI1PASSTHRU functions with the pins
      that were already defined.
      
      The notation used in the datasheet's multi-function pin table for the SoC is
      often creative: in this case the SYS* signals are enabled by a single bit,
      which is nothing unusual on its own, but in this case the bit was also
      participating in a multi-bit bitfield and therefore represented multiple
      functions. This fact was overlooked in the original patch.
      
      Fixes: 56e57cb6 (pinctrl: Add pinctrl-aspeed-g5 driver)
      Signed-off-by: NAndrew Jeffery <andrew@aj.id.au>
      Reviewed-by: NJoel Stanley <joel@jms.id.au>
      Acked-by: NRob Herring <robh@kernel.org>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      8eb37aff
    • A
      pinctrl: aspeed-g5: Fix GPIOE1 typo · d3dbabe9
      Andrew Jeffery 提交于
      This prevented C20 from successfully being muxed as GPIO.
      
      Fixes: 56e57cb6 (pinctrl: Add pinctrl-aspeed-g5 driver)
      Signed-off-by: NAndrew Jeffery <andrew@aj.id.au>
      Reviewed-by: NJoel Stanley <joel@jms.id.au>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      d3dbabe9
    • A
      pinctrl: aspeed-g5: Fix names of GPID2 pins · 97e8c3f5
      Andrew Jeffery 提交于
      Fixes simple typos in the initial commit. There is no behavioural
      change.
      
      Fixes: 56e57cb6 (pinctrl: Add pinctrl-aspeed-g5 driver)
      Reported-by: NXo Wang <xow@google.com>
      Signed-off-by: NAndrew Jeffery <andrew@aj.id.au>
      Reviewed-by: NJoel Stanley <joel@jms.id.au>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      97e8c3f5
    • A
      pinctrl: aspeed: "Not enabled" is a significant mux state · 5366f146
      Andrew Jeffery 提交于
      Consider a scenario with one pin P that has two signals A and B, where A
      is defined to be higher priority than B: That is, if the mux IP is in a
      state that would consider both A and B to be active on P, then A will be
      the active signal.
      
      To instead configure B as the active signal we must configure the mux so
      that A is inactive. The mux state for signals can be described by
      logical operations on one or more bits from one or more registers (a
      "signal expression"), which in some cases leads to aliased mux states for
      a particular signal. Further, signals described by multi-bit bitfields
      often do not only need to record the states that would make them active
      (the "enable" expressions), but also the states that makes them inactive
      (the "disable" expressions). All of this combined leads to four possible
      states for a signal:
      
               1. A signal is active with respect to an "enable" expression
               2. A signal is not active with respect to an "enable" expression
               3. A signal is inactive with respect to a "disable" expression
               4. A signal is not inactive with respect to a "disable" expression
      
      In the case of P, if we are looking to activate B without explicitly
      having configured A it's enough to consider A inactive if all of A's
      "enable" signal expressions evaluate to "not active". If any evaluate to
      "active" then the corresponding "disable" states must be applied so it
      becomes inactive.
      
      For example, on the AST2400 the pins composing GPIO bank H provide
      signals ROMD8 through ROMD15 (high priority) and those for UART6 (low
      priority). The mux states for ROMD8 through ROMD15 are aliased, i.e.
      there are two mux states that result in the respective signals being
      configured:
      
               A. SCU90[6]=1
               B. Strap[4,1:0]=100
      
      Further, the second mux state is a 3-bit bitfield that explicitly
      defines the enabled state but the disabled state is implicit, i.e. if
      Strap[4,1:0] is not exactly "100" then ROMD8 through ROMD15 are not
      considered active. This requires the mux function evaluation logic to
      use approach 2. above, however the existing code was using approach 3.
      The problem was brought to light on the Palmetto machines where the
      strap register value is 0x120ce416, and prevented GPIO requests in bank
      H from succeeding despite the hardware being in a position to allow
      them.
      
      Fixes: 318398c09a8d ("pinctrl: Add core pinctrl support for Aspeed SoCs")
      Signed-off-by: NAndrew Jeffery <andrew@aj.id.au>
      Reviewed-by: NJoel Stanley <joel@jms.id.au>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      5366f146
    • P
      locking, fs/locks: Add missing file_sem locks · 5f43086b
      Peter Zijlstra 提交于
      I overlooked a few code-paths that can lead to
      locks_delete_global_locks().
      Reported-by: NDmitry Vyukov <dvyukov@google.com>
      Signed-off-by: NPeter Zijlstra (Intel) <peterz@infradead.org>
      Reviewed-by: NJeff Layton <jlayton@poochiereds.net>
      Cc: Al Viro <viro@zeniv.linux.org.uk>
      Cc: Bruce Fields <bfields@fieldses.org>
      Cc: Linus Torvalds <torvalds@linux-foundation.org>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: linux-fsdevel@vger.kernel.org
      Cc: syzkaller <syzkaller@googlegroups.com>
      Link: http://lkml.kernel.org/r/20161008081228.GF3142@twins.programming.kicks-ass.netSigned-off-by: NIngo Molnar <mingo@kernel.org>
      5f43086b