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    • F
      MIPS: BCM63xx: Fix SPI message control register handling for BCM6338/6348. · 5a670445
      Florian Fainelli 提交于
      BCM6338 and BCM6348 have a message control register width of 8 bits, instead
      of 16-bits like what the SPI driver assumes right now. Also the SPI message
      type shift value of 14 is actually 6 for these SoCs.
      This resulted in transmit FIFO corruption because we were writing 16-bits
      to an 8-bits wide register, thus spanning on the first byte of the transmit
      FIFO, which had already been filed in bcm63xx_spi_fill_txrx_fifo().
      
      Fix this by passing the message control register width and message type
      shift through platform data back to the SPI driver so that it can use
      it properly.
      Signed-off-by: NFlorian Fainelli <florian@openwrt.org>
      Cc: linux-mips@linux-mips.org
      Cc: grant.likely@secretlab.ca
      Cc: spi-devel-general@lists.sourceforge.net
      Cc: jonas.gorski@gmail.com
      Patchwork: https://patchwork.linux-mips.org/patch/3983/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      5a670445
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