1. 29 8月, 2013 1 次提交
  2. 03 6月, 2013 1 次提交
    • A
      spi: sirf: avoid uninitialized-use warning · 804ae438
      Arnd Bergmann 提交于
      24778be2 "spi: convert drivers to use bits_per_word_mask"
      removed the "default" statement in the spi_sirfsoc_setup_transfer
      switch, causing a new warning:
      
      drivers/spi/spi-sirf.c: In function 'spi_sirfsoc_setup_transfer':
      arch/arm/include/asm/io.h:90:2: warning: 'rxfifo_ctrl' may be used uninitialized in this function [-Wmaybe-uninitialized]
        asm volatile("str %1, %0"
        ^
      drivers/spi/spi-sirf.c:364:19: note: 'rxfifo_ctrl' was declared here
        u32 txfifo_ctrl, rxfifo_ctrl;
                         ^
      
      The compiler has correctly identified that this case may happen,
      but since we know that things are horribly broken if bits_per_word
      is ever something other than the values we tested, calling BUG()
      is an appropriate action and tells the compiler that execution
      will not continue afterwards.
      Signed-off-by: NArnd Bergmann <arnd@arndb.de>
      Cc: Stephen Warren <swarren@wwwdotorg.org>
      Cc: Mark Brown <broonie@kernel.org>
      Signed-off-by: NMark Brown <broonie@linaro.org>
      804ae438
  3. 30 5月, 2013 1 次提交
  4. 21 5月, 2013 1 次提交
    • Q
      spi: sirf: fix the issue while transferring more than 256 words · 237ce466
      Qipan Li 提交于
      currently, spi irq handler only does rx processing and fetching data from rx
      fifo when "FRM_END" irq happens. FRM_END indicates one transfer completes. if
      rx size is less than 256, it works well.
      but the problem is that spi rx fifo size is only 256 bytes, then if data size
      of one frame is more than 256, before FRM_END comes, rx fifo will be filled with
      RXFIFO_OFLOW overflow interrupt, it will make us lose some data due to fifo
      overflow.
      Explicitly we need do fetch work from device rx fifo in irq handler not only in
      "FRM_END" irq but also in "THD_REACH" irq. THD_REACH means rx fifo has come to
      its threshold and will come to overflow if we don't take data from it in time.
      
      In this patch, we fix this issue. we take data from rx fifo when either FRM_END
      or RX_THD_REACH irq comes, we put data into tx fifo when either TX_FIFO_EMPTY
      or TX_THD_REACH irq comes.
      Signed-off-by: NQipan Li <Qipan.Li@csr.com>
      Signed-off-by: NZhiwu Song <Zhiwu.Song@csr.com>
      Signed-off-by: NBarry Song <Baohua.Song@csr.com>
      Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
      237ce466
  5. 13 5月, 2013 1 次提交
  6. 24 4月, 2013 1 次提交
  7. 05 2月, 2013 3 次提交
  8. 26 1月, 2013 1 次提交
  9. 08 12月, 2012 1 次提交
  10. 20 5月, 2012 1 次提交
  11. 10 3月, 2012 1 次提交