- 12 11月, 2015 4 次提交
-
-
由 Huaitong Han 提交于
KVM uses the get_xsave_addr() function in a different fashion from the native kernel, in that the 'xsave' parameter belongs to guest vcpu, not the currently running task. But 'xsave' is replaced with current task's (host) xsave structure, so get_xsave_addr() will incorrectly return the bad xsave address to KVM. Fix it so that the passed in 'xsave' address is used - as intended originally. Signed-off-by: NHuaitong Han <huaitong.han@intel.com> Reviewed-by: NDave Hansen <dave.hansen@linux.intel.com> Cc: <stable@vger.kernel.org> Cc: Andy Lutomirski <luto@amacapital.net> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Borislav Petkov <bp@alien8.de> Cc: Fenghua Yu <fenghua.yu@intel.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Oleg Nesterov <oleg@redhat.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Quentin Casasnovas <quentin.casasnovas@oracle.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: dave.hansen@intel.com Link: http://lkml.kernel.org/r/1446800423-21622-1-git-send-email-huaitong.han@intel.com [ Tidied up the changelog. ] Signed-off-by: NIngo Molnar <mingo@kernel.org>
-
由 Dave Hansen 提交于
(This should have gone to LKML originally. Sorry for the extra noise, folks on the cc.) Background: Signal frames on x86 have two formats: 1. For 32-bit executables (whether on a real 32-bit kernel or under 32-bit emulation on a 64-bit kernel) we have a 'fpregset_t' that includes the "FSAVE" registers. 2. For 64-bit executables (on 64-bit kernels obviously), the 'fpregset_t' is smaller and does not contain the "FSAVE" state. When creating the signal frame, we have to be aware of whether we are running a 32 or 64-bit executable so we create the correct format signal frame. Problem: save_xstate_epilog() uses 'fx_sw_reserved_ia32' whenever it is called for a 32-bit executable. This is for real 32-bit and ia32 emulation. But, fpu__init_prepare_fx_sw_frame() only initializes 'fx_sw_reserved_ia32' when emulation is enabled, *NOT* for real 32-bit kernels. This leads to really wierd situations where 32-bit programs lose their extended state when returning from a signal handler. The kernel copies the uninitialized (zero) 'fx_sw_reserved_ia32' out to userspace in save_xstate_epilog(). But when returning from the signal, the kernel errors out in check_for_xstate() when it does not see FP_XSTATE_MAGIC1 present (because it was zeroed). This leads to the FPU/XSAVE state being initialized. For MPX, this leads to the most permissive state and means we silently lose bounds violations. I think this would also mean that we could lose *ANY* FPU/SSE/AVX state. I'm not sure why no one has spotted this bug. I believe this was broken by: 72a671ce ("x86, fpu: Unify signal handling code paths for x86 and x86_64 kernels") way back in 2012. Signed-off-by: NDave Hansen <dave.hansen@linux.intel.com> Cc: <stable@vger.kernel.org> Cc: Andy Lutomirski <luto@amacapital.net> Cc: Borislav Petkov <bp@alien8.de> Cc: Brian Gerst <brgerst@gmail.com> Cc: Denys Vlasenko <dvlasenk@redhat.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: dave@sr71.net Cc: fenghua.yu@intel.com Cc: yu-cheng.yu@intel.com Link: http://lkml.kernel.org/r/20151111002354.A0799571@viggo.jf.intel.comSigned-off-by: NIngo Molnar <mingo@kernel.org>
-
由 Dave Hansen 提交于
I received a bug report that running 32-bit MPX binaries on 64-bit kernels was broken. I traced it down to this little code snippet. We were switching our "number of bounds directory entries" calculation correctly. But, we didn't switch the other side of the calculation: the virtual space size. This meant that we were calculating an absurd size for bd_entry_virt_space() on 32-bit because we used the 64-bit virt_space. This was _also_ broken for 32-bit kernels running on 64-bit hardware since boot_cpu_data.x86_virt_bits=48 even when running in 32-bit mode. Correct that and properly handle all 3 possible cases: 1. 32-bit binary on 64-bit kernel 2. 64-bit binary on 64-bit kernel 3. 32-bit binary on 32-bit kernel This manifested in having bounds tables not properly unmapped. It "leaked" memory but had no functional impact otherwise. Signed-off-by: NDave Hansen <dave.hansen@linux.intel.com> Cc: <stable@vger.kernel.org> Cc: Andy Lutomirski <luto@amacapital.net> Cc: Borislav Petkov <bp@alien8.de> Cc: Brian Gerst <brgerst@gmail.com> Cc: Dave Hansen <dave@sr71.net> Cc: Denys Vlasenko <dvlasenk@redhat.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/20151111181934.FA7FAC34@viggo.jf.intel.comSigned-off-by: NIngo Molnar <mingo@kernel.org>
-
由 Dave Hansen 提交于
When you call get_user(foo, bar), you effectively do a copy_from_user(&foo, bar, sizeof(*bar)); Note that the sizeof() is implicit. When we reach out to userspace to try to zap an entire "bounds table" we need to go read a "bounds directory entry" in order to locate the table's address. The size of a "directory entry" depends on the binary being run and is always the size of a pointer. But, when we have a 64-bit kernel and a 32-bit application, the directory entry is still only 32-bits long, but we fetch it with a 64-bit pointer which makes get_user() does a 64-bit fetch. Reading 4 extra bytes isn't harmful, unless we are at the end of and run off the table. It might also cause the zero page to get faulted in unnecessarily even if you are not at the end. Fix it up by doing a special 32-bit get_user() via a cast when we have 32-bit userspace. Signed-off-by: NDave Hansen <dave.hansen@linux.intel.com> Cc: <stable@vger.kernel.org> Cc: Andy Lutomirski <luto@amacapital.net> Cc: Borislav Petkov <bp@alien8.de> Cc: Brian Gerst <brgerst@gmail.com> Cc: Dave Hansen <dave@sr71.net> Cc: Denys Vlasenko <dvlasenk@redhat.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/20151111181931.3ACF6822@viggo.jf.intel.comSigned-off-by: NIngo Molnar <mingo@kernel.org>
-
- 07 11月, 2015 6 次提交
-
-
由 Borislav Petkov 提交于
When we get loaded by a 64-bit bootloader, kernel entry point is startup_64 in head_64.S. We don't trust any and all bootloaders because some will fiddle with CPU configuration so we go ahead and massage each CPU into sanity again. For example, some dell BIOSes have this XD disable feature which set IA32_MISC_ENABLE[34] and disable NX. This might be some dumb workaround for other OSes but Linux sure doesn't need it. A similar thing is present in the Surface 3 firmware - see https://bugzilla.kernel.org/show_bug.cgi?id=106051 - which sets this bit only on the BSP: # rdmsr -a 0x1a0 400850089 850089 850089 850089 I know, right?! There's not even an off switch in there. So fix all those cases by sanitizing the 64-bit entry point too. For that, make verify_cpu() callable in 64-bit mode also. Requested-and-debugged-by: N"H. Peter Anvin" <hpa@zytor.com> Reported-and-tested-by: NBastien Nocera <bugzilla@hadess.net> Signed-off-by: NBorislav Petkov <bp@suse.de> Cc: Matt Fleming <matt@codeblueprint.co.uk> Cc: Peter Zijlstra <peterz@infradead.org> Cc: stable@vger.kernel.org Link: http://lkml.kernel.org/r/1446739076-21303-1-git-send-email-bp@alien8.deSigned-off-by: NThomas Gleixner <tglx@linutronix.de>
-
由 Krzysztof Mazur 提交于
The commit f5f3497c extended the low identity mapping. However, if the kernel uses more than 2 GB (VMSPLIT_2G_OPT or VMSPLIT_1G memory split), the normal memory mapping is overwritten by the low identity mapping causing a crash. To avoid overwritting, limit the low identity map to cover only memory before kernel range (PAGE_OFFSET). Fixes: f5f3497c "x86/setup: Extend low identity map to cover whole kernel range Signed-off-by: NKrzysztof Mazur <krzysiek@podlesie.net> Cc: Andy Lutomirski <luto@amacapital.net> Cc: Borislav Petkov <bp@alien8.de> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Matt Fleming <matt.fleming@intel.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: stable@vger.kernel.org Link: http://lkml.kernel.org/r/1446815916-22105-1-git-send-email-krzysiek@podlesie.netSigned-off-by: NThomas Gleixner <tglx@linutronix.de>
-
由 Boris Ostrovsky 提交于
The range between 0xffff800000000000 and 0xffff87ffffffffff is reserved for hypervisor and therefore we should not try to follow PGD's indexes corresponding to those addresses. While this has always been a problem, with the new W+X warning mechanism ptdump_walk_pgd_level_core() can now be called during boot, causing a PV Xen guest to crash. [ tglx: Replaced the macro with a readable inline ] Fixes: e1a58320 "x86/mm: Warn on W^X mappings" Reported-by: NSander Eikelenboom <linux@eikelenboom.it> Signed-off-by: NBoris Ostrovsky <boris.ostrovsky@oracle.com> Cc: xen-devel@lists.xen.org Link: http://lkml.kernel.org/r/1446749795-27764-1-git-send-email-boris.ostrovsky@oracle.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>
-
由 Aravind Gopalakrishnan 提交于
On AMD Fam17h systems, the last level cache is not resident in the northbridge. Therefore, we cannot assign cpu_llc_id to the same value as Node ID as we have been doing until now. We should rather look at the ApicID bits of the core to provide us the last level cache ID info. Signed-off-by: NAravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Andy Lutomirski <luto@kernel.org> Cc: Frederic Weisbecker <fweisbec@gmail.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Huang Rui <ray.huang@amd.com> Cc: Ingo Molnar <mingo@kernel.org> Cc: Jacob Shin <jacob.w.shin@gmail.com> Link: http://lkml.kernel.org/r/1446582899-9378-1-git-send-email-Aravind.Gopalakrishnan@amd.comSigned-off-by: NBorislav Petkov <bp@suse.de> Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
-
由 Vitaly Kuznetsov 提交于
Commit d32932d0 ("x86/irq: Convert IOAPIC to use hierarchical irqdomain interfaces") brought a regression for Hyper-V Gen2 instances. These instances don't have i8259 legacy PIC but they use legacy IRQs for serial port, rtc, and acpi. With this commit included we end up with these IRQs not initialized. Earlier, there was a special workaround for legacy IRQs in mp_map_pin_to_irq() doing mp_irqdomain_map() without looking at nr_legacy_irqs() and now we fail in __irq_domain_alloc_irqs() when irq_domain_alloc_descs() returns -EEXIST. The essence of the issue seems to be that early_irq_init() calls arch_probe_nr_irqs() to figure out the number of legacy IRQs before we probe for i8259 and gets 16. Later when init_8259A() is called we switch to NULL legacy PIC and nr_legacy_irqs() starts to return 0 but we already have 16 descs allocated. Solve the issue by separating i8259 probe from init and calling it in arch_probe_nr_irqs() before we actually use nr_legacy_irqs() information. Fixes: d32932d0 ("x86/irq: Convert IOAPIC to use hierarchical irqdomain interfaces") Signed-off-by: NVitaly Kuznetsov <vkuznets@redhat.com> Cc: Jiang Liu <jiang.liu@linux.intel.com> Cc: K. Y. Srinivasan <kys@microsoft.com> Cc: stable@vger.kernel.org Link: http://lkml.kernel.org/r/1446543614-3621-1-git-send-email-vkuznets@redhat.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>
-
由 Andy Shevchenko 提交于
The Intel Merrifield SoC is a successor of the Intel MID line of SoCs. Let's set the neccessary capability for that chip. See commit c54fdbb2 (x86: Add cpu capability flag X86_FEATURE_NONSTOP_TSC_S3) for the details. Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com> Link: http://lkml.kernel.org/r/1444319786-36125-1-git-send-email-andriy.shevchenko@linux.intel.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>
-
- 03 11月, 2015 17 次提交
-
-
由 Simon Guinot 提交于
Since DT support is now available for the LEDs found on the LaCie netxbig boards (Kirkwood-based), then the old-fashion netxbig board setup file is no longer needed. This patch removes this file. Signed-off-by: NSimon Guinot <simon.guinot@sequanux.org> Acked-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: NJacek Anaszewski <j.anaszewski@samsung.com>
-
由 Simon Guinot 提交于
This patch adds DT entries for the LEDs found on the Kirkwood-based LaCie boards 2Big and 5Big Network v2. Signed-off-by: NSimon Guinot <simon.guinot@sequanux.org> Acked-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: NJacek Anaszewski <j.anaszewski@samsung.com>
-
由 Ralf Baechle 提交于
Fixes the following randconfig problem leds-sead3.c:(.text+0x7dc): undefined reference to `led_classdev_unregister' leds-sead3.c:(.text+0x7e8): undefined reference to `led_classdev_unregister' Signed-off-by: NRalf Baechle <ralf@linux-mips.org> Cc: Bryan Wu <cooloney@gmail.com> Cc: Richard Purdie <rpurdie@rpsys.net> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-leds@vger.kernel.org Cc: linux-mips@linux-mips.org Signed-off-by: NJacek Anaszewski <j.anaszewski@samsung.com>
-
由 Alexandre Belloni 提交于
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: NHans-Christian Egtvedt <egtvedt@samfundet.no>
-
由 Guenter Roeck 提交于
Function get_cmos_time() was removed with commit 657926a83df9 ("cris: time: Cleanup of persistent clock stuff"). The remaining reference to it may cause the following build error. arch/cris/kernel/built-in.o:(___ksymtab+get_cmos_time+0x0): undefined reference to `get_cmos_time' Makefile:946: recipe for target 'vmlinux' failed Fixes: 657926a83df9 ("cris: time: Cleanup of persistent clock stuff") Cc: Xunlei Pang <pang.xunlei@linaro.org> Cc: Rabin Vincent <rabin@rab.in> Signed-off-by: NGuenter Roeck <linux@roeck-us.net> Signed-off-by: NJesper Nilsson <jespern@axis.com>
-
由 Jesper Nilsson 提交于
Drop all code related to Kconfigs that don't exist. Fix one Kconfig where it was actually typo:ed (ETRAX_KGB_PORT2) Drop content related to CRIS v32 SoCs from etraxgpio.h headerfile, all use of GPIO for both ETRAX FS and ARTPEC-3 should now be through standard gpiolib instead. Signed-off-by: NJesper Nilsson <jesper.nilsson@axis.com>
-
由 Xunlei Pang 提交于
- Remove update_persistent_clock(), as it does nothing now. - Remove read_persistent_clock(), let it fall back to the weak version. Cc: Mikael Starvik <starvik@axis.com> Cc: John Stultz <john.stultz@linaro.org> Cc: Arnd Bergmann <arnd@arndb.de> Signed-off-by: NXunlei Pang <pang.xunlei@linaro.org> Acked-by: NRabin Vincent <rabin@rab.in> Signed-off-by: NJesper Nilsson <jespern@axis.com>
-
由 Andy Shevchenko 提交于
There are native helpers such as print_hex_byte() and %*ph specifier to dump data in hex format. Re-use them instead of a custom approach. Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: NJesper Nilsson <jespern@axis.com>
-
由 Rabin Vincent 提交于
Since we now have a gpiolib driver, remove this code: The gpio-etraxfs driver (along with things like gpio-keys-polled for polling support) replaces the GIO driver implementations in mach-a3 and mach-fs. The various generic external chip drivers replace the "virtual gpio" parts. The generic gpio-leds driver replaces the LED handling. Signed-off-by: NRabin Vincent <rabin@rab.in> Signed-off-by: NJesper Nilsson <jespern@axis.com>
-
由 Rabin Vincent 提交于
Now that we have a gpiolib GPIO driver, the generic i2c-gpio driver provides this functionality. Signed-off-by: NRabin Vincent <rabin@rab.in> Signed-off-by: NJesper Nilsson <jespern@axis.com>
-
由 Rabin Vincent 提交于
Add a device tree for the Axis P1343 with the ARTPEC-3 SoC and on-board LEDs and RTC. Signed-off-by: NRabin Vincent <rabin@rab.in> Signed-off-by: NJesper Nilsson <jespern@axis.com>
-
由 Rabin Vincent 提交于
Add the GPIO driver to the device tree and, using it, support for the LEDs and the RTC chip (via I2C-GPIO), as well as the temperature sensor (via SPI-GPIO). Signed-off-by: NRabin Vincent <rabin@rab.in> Signed-off-by: NJesper Nilsson <jespern@axis.com>
-
由 Rabin Vincent 提交于
Add a dt-bindings symlink to get DT include files, as on other architectures. See c58299aa ("kbuild: create an "include chroot" for DT bindings") for the details. Signed-off-by: NRabin Vincent <rabin@rab.in> Signed-off-by: NJesper Nilsson <jespern@axis.com>
-
由 Rabin Vincent 提交于
Increase NR_IQRS so we can fit in GPIO interrupts. Signed-off-by: NRabin Vincent <rabin@rab.in> Signed-off-by: NJesper Nilsson <jespern@axis.com>
-
由 Chen Gang 提交于
Within one C file, current gcc can optimize the global static variables according to the C code, but it will skip assembly code -- it will pass them to gas directly. if the static variable is used between C code and assembly code in one C file (e.g. is_dyn_brkp in kgdb.c), it needs '__used' to let gcc know it should be still used, or gcc may remove it for optimization. The related error in this case: LD init/built-in.o arch/cris/arch-v10/kernel/built-in.o: In function `kgdb_handle_breakpoint': (.text+0x2aca): undefined reference to `is_dyn_brkp' arch/cris/arch-v10/kernel/built-in.o: In function `is_static': kgdb.c:(.text+0x2ada): undefined reference to `is_dyn_brkp' Signed-off-by: NChen Gang <gang.chen.5i5j@gmail.com> Signed-off-by: NJesper Nilsson <jespern@axis.com>
-
由 Chen Gang 提交于
For arch-v10, there is no DTP0 register, and at present, assembler know BAR, so use BAR instead of DTP0, the related error (with allmodconfig): CC arch/cris/arch-v10/kernel/kgdb.o {standard input}: Assembler messages: {standard input}:6: Error: Illegal operands {standard input}:6: Error: Illegal operands Signed-off-by: NChen Gang <gang.chen.5i5j@gmail.com> Acked-by: NHans-Peter Nilsson <hp@axis.com> Signed-off-by: NJesper Nilsson <jespern@axis.com>
-
由 Andy Shevchenko 提交于
There are kernel native helpers to convert hex ascii to the binary format: hex_to_bin() and hex2bin(). Thus, no need to reimplement them customly. Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: NJesper Nilsson <jespern@axis.com>
-
- 01 11月, 2015 3 次提交
-
-
由 Wan Zongshun 提交于
AMD Fam17h processors introduce support for the CLZERO instruction. It zeroes out the 64 byte cache line specified in RAX. Add the bit here to allow /proc/cpuinfo to list the feature. Boris: we're adding this as a separate ->x86_capability leaf because CPUID_80000008_EBX is going to contain more feature bits and it will fill out with time. Signed-off-by: NWan Zongshun <Vincent.Wan@amd.com> Signed-off-by: NAravind Gopalakrishnan <aravind.gopalakrishnan@amd.com> [ Wrap code in patch form, fix comments. ] Signed-off-by: NBorislav Petkov <bp@suse.de> Cc: Andy Lutomirski <luto@kernel.org> Cc: Borislav Petkov <bp@alien8.de> Cc: Denys Vlasenko <dvlasenk@redhat.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Huang Rui <ray.huang@amd.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Tony Luck <tony.luck@intel.com> Link: http://lkml.kernel.org/r/1446207099-24948-4-git-send-email-bp@alien8.deSigned-off-by: NIngo Molnar <mingo@kernel.org>
-
由 Borislav Petkov 提交于
Caught by building with W= which enable -Wswitch-default also. Signed-off-by: NBorislav Petkov <bp@suse.de> Cc: Borislav Petkov <bp@alien8.de> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Tony Luck <tony.luck@intel.com> Link: http://lkml.kernel.org/r/1446207099-24948-3-git-send-email-bp@alien8.deSigned-off-by: NIngo Molnar <mingo@kernel.org>
-
由 Aravind Gopalakrishnan 提交于
Scalable MCA (SMCA) is a new feature in AMD Fam17h processors which indicates presence of MCA extensions. MCA extensions expands existing register space for the MCE banks and also introduces a new MSR range to accommodate new banks. Add the detection bit. Signed-off-by: NAravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com> [ Reformat mce_vendor_flags definitions and save indentation levels. Improve comments. ] Signed-off-by: NBorislav Petkov <bp@suse.de> Cc: Ashok Raj <ashok.raj@intel.com> Cc: Borislav Petkov <bp@alien8.de> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Tony Luck <tony.luck@intel.com> Cc: linux-edac <linux-edac@vger.kernel.org> Link: http://lkml.kernel.org/r/1446207099-24948-2-git-send-email-bp@alien8.deSigned-off-by: NIngo Molnar <mingo@kernel.org>
-
- 31 10月, 2015 1 次提交
-
-
由 Andy Lutomirski 提交于
thread.vm86 points to per-task information -- the pointer should not be copied on clone. Fixes: d4ce0f26 ("x86/vm86: Move fields from 'struct kernel_vm86_struct' to 'struct vm86'") Signed-off-by: NAndy Lutomirski <luto@kernel.org> Cc: Brian Gerst <brgerst@gmail.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Borislav Petkov <bp@alien8.de> Cc: Stas Sergeev <stsp@list.ru> Link: http://lkml.kernel.org/r/71c5d6985d70ec8197c8d72f003823c81b7dcf99.1446270067.git.luto@kernel.orgSigned-off-by: NThomas Gleixner <tglx@linutronix.de>
-
- 30 10月, 2015 1 次提交
-
-
由 Ard Biesheuvel 提交于
The current arm64 Image relocation code in the UEFI stub assumes that the dram_base argument it receives is always a multiple of 2 MB. In reality, it is simply the lowest start address of all RAM entries in the UEFI memory map, which means it could be any multiple of 4 KB. Since the arm64 kernel Image needs to reside TEXT_OFFSET bytes beyond a 2 MB aligned base, or it will fail to boot, make sure we round dram_base to 2 MB before using it to calculate the relocation address. Fixes: e38457c3 ("arm64: efi: prefer AllocatePages() over efi_low_alloc() for vmlinux") Reported-by: NTimur Tabi <timur@codeaurora.org> Tested-by: NTimur Tabi <timur@codeaurora.org> Acked-by: NMark Rutland <mark.rutland@arm.com> Signed-off-by: NArd Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: NWill Deacon <will.deacon@arm.com>
-
- 29 10月, 2015 6 次提交
-
-
由 H. Nikolaus Schaller 提交于
Commit 8a603f91 ("ARM: 8445/1: fix vdsomunge not to depend on glibc specific byteswap.h") unfortunately introduced a bug created but not found during discussion and patch simplification. Reported-by: NEfraim Yawitz <efraim.yawitz@gmail.com> Signed-off-by: NH. Nikolaus Schaller <hns@goldelico.com> Fixes: 8a603f91 ("ARM: 8445/1: fix vdsomunge not to depend on glibc specific byteswap.h") Signed-off-by: NNathan Lynch <nathan_lynch@mentor.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
-
由 Vineet Gupta 提交于
This is the first working implementation of 40-bit physical address extension on ARCv2. Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com> Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
-
由 Émeric MASCHINO 提交于
systemd > 218 fails to compile on ia64 with: error: ‘__NR_kcmp’ undeclared [1]. I've been told that this is because the kcmp syscall hasn't been wired up for the ia64 arch [2]. The proposed patch thus wire up the kcmp syscall for the ia64 arch. [1] https://bugs.gentoo.org/show_bug.cgi?id=560492 [2] https://bugs.gentoo.org/show_bug.cgi?id=560492#c17Signed-off-by: NÉmeric MASCHINO <emeric.maschino@gmail.com> Signed-off-by: NTony Luck <tony.luck@intel.com>
-
由 Will Deacon 提交于
This reverts commit e306dfd0. With this patch applied, we were the only architecture making this sort of adjustment to the PC calculation in the unwinder. This causes problems for ftrace, where the PC values are matched against the contents of the stack frames in the callchain and fail to match any records after the address adjustment. Whilst there has been some effort to change ftrace to workaround this, those patches are not yet ready for mainline and, since we're the odd architecture in this regard, let's just step in line with other architectures (like arch/arm/) for now. Cc: <stable@vger.kernel.org> Signed-off-by: NWill Deacon <will.deacon@arm.com>
-
由 Lorenzo Pieralisi 提交于
Commit dd006da2 ("arm64: mm: increase VA range of identity map") introduced a mechanism to extend the virtual memory map range to support arm64 systems with system RAM located at very high offset, where the identity mapping used to enable/disable the MMU requires additional translation levels to map the physical memory at an equal virtual offset. The kernel detects at boot time the tcr_el1.t0sz value required by the identity mapping and sets-up the tcr_el1.t0sz register field accordingly, any time the identity map is required in the kernel (ie when enabling the MMU). After enabling the MMU, in the cold boot path the kernel resets the tcr_el1.t0sz to its default value (ie the actual configuration value for the system virtual address space) so that after enabling the MMU the memory space translated by ttbr0_el1 is restored as expected. Commit dd006da2 ("arm64: mm: increase VA range of identity map") also added code to set-up the tcr_el1.t0sz value when the kernel resumes from low-power states with the MMU off through cpu_resume() in order to effectively use the identity mapping to enable the MMU but failed to add the code required to restore the tcr_el1.t0sz to its default value, when the core returns to the kernel with the MMU enabled, so that the kernel might end up running with tcr_el1.t0sz value set-up for the identity mapping which can be lower than the value required by the actual virtual address space, resulting in an erroneous set-up. This patchs adds code in the resume path that restores the tcr_el1.t0sz default value upon core resume, mirroring this way the cold boot path behaviour therefore fixing the issue. Cc: <stable@vger.kernel.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Fixes: dd006da2 ("arm64: mm: increase VA range of identity map") Acked-by: NArd Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: NJames Morse <james.morse@arm.com> Signed-off-by: NWill Deacon <will.deacon@arm.com>
-
由 Will Deacon 提交于
If the STXR instruction fails in the SWP emulation code, we leave *data overwritten with the loaded value, therefore corrupting the data written by a subsequent, successful attempt. This patch re-jigs the code so that we only write back to *data once we know that the update has happened. Cc: <stable@vger.kernel.org> Fixes: bd35a4ad ("arm64: Port SWP/SWPB emulation support from arm") Reported-by: NShengjiu Wang <shengjiu.wang@freescale.com> Reported-by: NVladimir Murzin <vladimir.murzin@arm.com> Signed-off-by: NWill Deacon <will.deacon@arm.com>
-
- 28 10月, 2015 2 次提交
-
-
由 Vineet Gupta 提交于
Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
-
由 Vineet Gupta 提交于
That way a single flip of phys_addr_t to 64 bit ensures all places dealing with physical addresses get correct data Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
-