To simplify matching of DTS files of all NXP LPC32xx powered boards by
a file name add 'lpc3250' prefix to PHYTEC PHYCORE-LPC3250 board dts
file.
Acked-by: NSylvain Lemieux <slemieux.tyco@gmail.com>
Signed-off-by: NVladimir Zapolskiy <vz@mleia.com>

To declare MTD OF partitions NAND controller device node should have
a special 'partitions' subnode, the change removes a debug message
from mtd/ofpart on boot:

  nxp_lpc3220_slc: 'partitions' subnode not found on /ahb/flash@20020000.
  Trying to parse direct subnodes as partitions.
Acked-by: NSylvain Lemieux <slemieux.tyco@gmail.com>
Signed-off-by: NVladimir Zapolskiy <vz@mleia.com>

The change simplifies layout of PHY3250 board description by
referencing device nodes of LPC32xx controllers by label.

No functional change intended.
Acked-by: NSylvain Lemieux <slemieux.tyco@gmail.com>
Signed-off-by: NVladimir Zapolskiy <vz@mleia.com>

To simplify matching of DTS files of all NXP LPC32xx powered boards by
a file name add 'lpc3250' prefix to Embedded Artists LPC3250 board dts
file.
Acked-by: NSylvain Lemieux <slemieux.tyco@gmail.com>
Signed-off-by: NVladimir Zapolskiy <vz@mleia.com>

There is no 'at' hardware vendor defined yet, correct vendor prefix
for Atmel is 'atmel'.
Acked-by: NSylvain Lemieux <slemieux.tyco@gmail.com>
Signed-off-by: NVladimir Zapolskiy <vz@mleia.com>

To declare MTD OF partitions NAND controller device node should have
a special 'partitions' subnode, the change removes a debug message
from mtd/ofpart on boot:

  nxp_lpc3220_slc: 'partitions' subnode not found on /ahb/flash@20020000.
  Trying to parse direct subnodes as partitions.
Acked-by: NSylvain Lemieux <slemieux.tyco@gmail.com>
Signed-off-by: NVladimir Zapolskiy <vz@mleia.com>

The change simplifies layout of EA3250 board description by
referencing device nodes of LPC32xx controllers by label.

No functional change intended.
Acked-by: NSylvain Lemieux <slemieux.tyco@gmail.com>
Signed-off-by: NVladimir Zapolskiy <vz@mleia.com>

The change adds separate device nodes for SIC1 and SIC2 interrupt
controllers and reparents all defined SIC1 and SIC2 interrupt
producers to the correspondent interrupt controller, this is needed to
perform switching to a new LPC32xx MIC/SIC interrupt controller driver.
Acked-by: NSylvain Lemieux <slemieux.tyco@gmail.com>
Signed-off-by: NVladimir Zapolskiy <vz@mleia.com>

As the watchdog timer needs the slow clock, add it to the currently defined
wdt node.
Reported-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>

Add the SAMA5D2-Compatible Shutdown Controller node to sama5d2.dtsi
and the use of it in the sama5d2 Xplained board dts file.

Enable the RTC wakeup event and the "wake up" button support through the
input "0" that is present on the board.
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

The "interrupts" property is missing from the watchdog node. Add it with
highest priority value of 7.
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

clk_get() on a disabled clock node will return -EPROBE_DEFER, which can
cause drivers to be deferred forever if such clocks are referenced in
their devices' clocks properties.

Update the various disabled external clock nodes to default to a
frequency of 0, but don't disable them, to prevent this.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

clk_get() on a disabled clock node will return -EPROBE_DEFER, which can
cause drivers to be deferred forever if such clocks are referenced in
their devices' clocks properties.

Update the various disabled external clock nodes to default to a
frequency of 0, but don't disable them, to prevent this.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

clk_get() on a disabled clock node will return -EPROBE_DEFER, which can
cause drivers to be deferred forever if such clocks are referenced in
their devices' clocks properties.

Update the various disabled external clock nodes to default to a
frequency of 0, but don't disable them, to prevent this.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

clk_get() on a disabled clock node will return -EPROBE_DEFER, which can
cause drivers to be deferred forever if such clocks are referenced in
their devices' clocks properties.

Update the various disabled external clock nodes to default to a
frequency of 0, but don't disable them, to prevent this.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

clk_get() on a disabled clock node will return -EPROBE_DEFER, which can
cause drivers to be deferred forever if such clocks are referenced in
their devices' clocks properties.

Update the various disabled external clock nodes to default to a
frequency of 0, but don't disable them, to prevent this.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

This aligns with the internal configuration.
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>

Doing so saves quite a bit of code in the driver.

For more information on the 'reserved-memory' bindings see:

  Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
Suggested-by: NSuman Anna <s-anna@ti.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>

Signed-off-by: NLudovic Barre <ludovic.barre@st.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>

This patch supplies the Mailbox Controller nodes.  In order to
request channels, these nodes will be referenced by Mailbox
Client nodes.
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>

This is used for CPU Frequency Scaling.
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>

Used for Voltage Scaling using CPUFreq.
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>

Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>

You'll notice that the voltage cell is populated with 0's.  Voltage
information is very platform specific, even depends on 'cut' and
'substrate' versions.  Thus it is left blank for a generic (safe)
implementation.  If other nodes/properties are provided by the
bootloader, the ST CPUFreq driver will over-ride these generic
values.
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>

Application Notes 399 and 400 shares the same memory map and
features. Both are shipped with Cortex-M7 and have the same  peripheral
as AN385/AN386, but with different location of PSRAM and Ethernet
controller.
Signed-off-by: NVladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>

Application Notes 385 and 386 shares the same memory map and features
except the CPU is used. AN385 is supplied with Cortex-M3 CPU and AN386
is supplied with Cortex-M4.
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NVladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>

Fix a typo on PIN_PD24 for UTXD2 and FLEXCOM4_IO3 which were
wrongly linked to PIN_PD23).
Signed-off-by: NFlorian Vallee <fvallee@eukrea.fr>
Fixes: 7f16cb67 ("ARM: at91/dt: add sama5d2 pinmux")
Cc: stable@vger.kernel.org # v4.4+
[nicolas.ferre@atmel.com: add commit message, changed subject]
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Add Western Digital My Book World Edition device tree based on
Oxford Semiconductor OX810SE SoC.
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>

Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>

The VExpress development platform has an external expansion bus which
can be used for additional hardware (e.g. LogicTile Express daughter
boards).

Add this bus to the VExpress CoreTile device-trees.The bus is described
for a CoreTile occupying site 1.
Acked-by: NLiviu Dudau <Liviu.Dudau@arm.com>
Signed-off-by: NBrian Starkey <brian.starkey@arm.com>
Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>

Commit b9937347 ("scripts/dtc: Update to upstream version 53bf130b1cdd")
added warnings on node name unit-address presence/absence mismatch in
the device trees.

This patch fixes those warning on all the vexpress platforms where
unit-address is present in node name while the reg/ranges property is
not present.
Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>

Includes regulator and pin assignments.
Signed-off-by: NUlrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Same as on r8a7791.
Signed-off-by: NUlrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

The wrong values come from an old datasheet (H2 v0.6). Anything later
has the fixed value of 195MHz (H2 v0.7 up to Gen2-common V2.0).
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add a GPIO key with wake-up capability for the NMI button.
This allows to wake up the system from s2ram without relying on the
buttons on the optional switch board.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add the "1v8" pinctrl state and sd-uhs-sdr50 property to SDHI{0,2}.
Signed-off-by: NBen Hutchings <ben.hutchings@codethink.co.uk>
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

The clock binding for the main clock controller was changed to an
indexed controller style binding on request of the clk
maintainers. This updates the dtsi to use the new bindings.
Signed-off-by: NLars Persson <larper@axis.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

This commit adds pin-mux nodes for the NAND controller.
Some SoCs support 2 chip selects and the others only support
1 chip select.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Controller is present on every BCM4708* board but only few devices have
serial flash attached so mark it as disabled by default.
Signed-off-by: NRafał Miłecki <zajec5@gmail.com>
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

The SSP0/SPI1 and SSP1/SPI2 shared pinout and should be disable by
default.

Board specific dts should enable them, as needed.
Signed-off-by: NSylvain Lemieux <slemieux@tycoint.com>
Signed-off-by: NVladimir Zapolskiy <vz@mleia.com>