- 02 12月, 2016 1 次提交
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由 Tomasz Nowicki 提交于
This patch provides APEI arch-specific bits for ARM64 Meanwhile, (1) Move HEST type (ACPI_HEST_TYPE_IA32_CORRECTED_CHECK) checking to a generic place. (2) Select HAVE_ACPI_APEI when EFI and ACPI is set on ARM64, because arch_apei_get_mem_attribute is using efi_mem_attributes() on ARM64. Signed-off-by: NTomasz Nowicki <tomasz.nowicki@linaro.org> Tested-by: NJonathan (Zhixiong) Zhang <zjzhang@codeaurora.org> Signed-off-by: NFu Wei <fu.wei@linaro.org> [ Fu Wei: improve && upstream ] Acked-by: NHanjun Guo <hanjun.guo@linaro.org> Tested-by: NTyler Baicar <tbaicar@codeaurora.org> Acked-by: NWill Deacon <will.deacon@arm.com> Reviewed-by: NBorislav Petkov <bp@suse.de> Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
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- 23 7月, 2014 2 次提交
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由 Tomasz Nowicki 提交于
GHES currently maps two pages with atomic_ioremap. From now on, NMI is architectural depended so there is no need to allocate an NMI page for platforms without NMI support. To make it possible to not use a second page, swap the existing page order so that the IRQ context page is first, and the optional NMI context page is second. Then, use HAVE_ACPI_APEI_NMI to decide how many pages are to be allocated. Signed-off-by: NTomasz Nowicki <tomasz.nowicki@linaro.org> Acked-by: NBorislav Petkov <bp@suse.de> Signed-off-by: NTony Luck <tony.luck@intel.com>
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由 Tomasz Nowicki 提交于
This commit abstracts MCE calls and provides weak corresponding default implementation for those architectures which do not need arch specific actions. Each platform willing to do additional architectural actions should provides desired function definition. It allows us to avoid wrap code into #ifdef in generic code and prevent new platform from introducing dummy stub function too. Initially, there are two APEI arch-specific calls: - arch_apei_enable_cmcff() - arch_apei_report_mem_error() Both interact with MCE driver for X86 architecture. Signed-off-by: NTomasz Nowicki <tomasz.nowicki@linaro.org> Acked-by: NBorislav Petkov <bp@suse.de> Signed-off-by: NTony Luck <tony.luck@intel.com>
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