1. 01 10月, 2005 3 次提交
  2. 30 9月, 2005 2 次提交
  3. 28 9月, 2005 10 次提交
  4. 27 9月, 2005 6 次提交
  5. 23 9月, 2005 1 次提交
  6. 21 9月, 2005 1 次提交
  7. 06 9月, 2005 1 次提交
  8. 29 8月, 2005 3 次提交
  9. 17 8月, 2005 1 次提交
  10. 26 6月, 2005 1 次提交
    • R
      [PATCH] ppc64: kexec support for ppc64 · fce0d574
      R Sharada 提交于
      This patch implements the kexec support for ppc64 platforms.
      
      A couple of notes:
      
      1)  We copy the pages in virtual mode, using the full base kernel
          and a statically allocated stack.   At kexec_prepare time we
          scan the pages and if any overlap our (0, _end[]) range we
          return -ETXTBSY.
      
          On PowerPC 64 systems running in LPAR (logical partitioning)
          mode, only a small region of memory, referred to as the RMO,
          can be accessed in real mode.  Since Linux runs with only one
          zone of memory in the memory allocator, and it can be orders of
          magnitude more memory than the RMO, looping until we allocate
          pages in the source region is not feasible.  Copying in virtual
          means we don't have to write a hash table generation and call
          hypervisor to insert translations, instead we rely on the pinned
          kernel linear mapping.  The kernel already has move to linked
          location built in, so there is no requirement to load it at 0.
      
          If we want to load something other than a kernel, then a stub
          can be written to copy a linear chunk in real mode.
      
      2)  The start entry point gets passed parameters from the kernel.
          Slaves are started at a fixed address after copying code from
          the entry point.
      
          All CPUs get passed their firmware assigned physical id in r3
          (most calling conventions use this register for the first
          argument).
      
          This is used to distinguish each CPU from all other CPUs.
          Since firmware is not around, there is no other way to obtain
          this information other than to pass it somewhere.
      
          A single CPU, referred to here as the master and the one executing
          the kexec call, branches to start with the address of start in r4.
          While this can be calculated, we have to load it through a gpr to
          branch to this point so defining the register this is contained
          in is free.  A stack of unspecified size is available at r1
          (also common calling convention).
      
          All remaining running CPUs are sent to start at absolute address
          0x60 after copying the first 0x100 bytes from start to address 0.
          This convention was chosen because it matches what the kernel
          has been doing itself.  (only gpr3 is defined).
      
          Note: This is not quite the convention of the kexec bootblock v2
          in the kernel.  A stub has been written to convert between them,
          and we may adjust the kernel in the future to allow this directly
          without any stub.
      
      3)  Destination pages can be placed anywhere, even where they
          would not be accessible in real mode.  This will allow us to
          place ram disks above the RMO if we choose.
      Signed-off-by: NMilton Miller <miltonm@bga.com>
      Signed-off-by: NR Sharada <sharada@in.ibm.com>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      fce0d574
  11. 23 6月, 2005 4 次提交
    • A
      [PATCH] ppc64: Add driver for BPA iommu · ae209cf1
      Arnd Bergmann 提交于
      Implementation of software load support for the BE iommu. This is very
      different from other iommu code on ppc64, since we only do a static mapping.
      The mapping is currently hardcoded but should really be read from the
      firmware, but they don't set up the device nodes yet. There is a single
      512MB DMA window for PCI, USB and ethernet at 0x20000000 for our RAM.
      
      The Cell processor can put the I/O page table either in memory like
      the hashed page table (hardware load) or have the operating system
      write the entries into memory mapped CPU registers (software load).
      
      I use the software load mechanism because I know that all I/O page
      table entries for the amount of installed physical memory fit into
      the IO TLB cache. At the point when we get machines with more than
      4GB of installed memory, we can either use hardware I/O page table
      access like the other platforms do or dynamically update the I/O
      TLB entries when a page fault occurs in the I/O subsystem.
      
      The software load can then use the macros that I have implemented
      for the static mapping in order to do the TLB cache updates.
      Signed-off-by: NArnd Bergmann <arndb@de.ibm.com>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      ae209cf1
    • A
      [PATCH] ppc64: Add driver for BPA interrupt controllers · cebf589c
      Arnd Bergmann 提交于
      Add support for the integrated interrupt controller on BPA
      CPUs. There is one of those for each SMT thread.
      
      The mapping of interrupt numbers to HW interrupt sources
      is described in arch/ppc64/kernel/bpa_iic.h.
      
      This version hardcodes the 'Spider' chip as the secondary
      interrupt controller. That is not really generic for the
      architecture, but at the moment it is the only secondary
      PIC that exists.
      
      A little more work will be needed on this as soon as
      we have boards with multiple external interrupt controllers.
      Signed-off-by: NArnd Bergmann <arndb@de.ibm.com>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      cebf589c
    • A
      [PATCH] ppc64: add BPA platform type · fef1c772
      Arnd Bergmann 提交于
      This adds the basic support for running on BPA machines.
      So far, this is only the IBM workstation, and it will
      not run on others without a little more generalization.
      
      It should be possible to configure a kernel for any
      combination of CONFIG_PPC_BPA with any of the other
      multiplatform targets.
      Signed-off-by: NArnd Bergmann <arndb@de.ibm.com>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      fef1c772
    • A
      [PATCH] ppc64: Split out generic rtas code from pSeries_pci.c. · c5a3c2e5
      Arnd Bergmann 提交于
      BPA is using rtas for PCI but should not be confused by
      pSeries code. This also avoids some #ifdefs. Other
      platforms that want to use rtas_pci.c could create
      their own platform_pci.c with platform specific fixups.
      Signed-off-by: NArnd Bergmann <arndb@de.ibm.com>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      c5a3c2e5
  12. 22 6月, 2005 4 次提交
  13. 17 4月, 2005 1 次提交
    • L
      Linux-2.6.12-rc2 · 1da177e4
      Linus Torvalds 提交于
      Initial git repository build. I'm not bothering with the full history,
      even though we have it. We can create a separate "historical" git
      archive of that later if we want to, and in the meantime it's about
      3.2GB when imported into git - space that would just make the early
      git days unnecessarily complicated, when we don't have a lot of good
      infrastructure for it.
      
      Let it rip!
      1da177e4