Use the new zynq binding for macb ethernet, since it will disable half
duplex gigabit like the Zynq TRM says to do.
Signed-off-by: NNathan Sullivan <nathan.sullivan@ni.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Based on:
"devicetree: Add Cadence WDT devicetree bindings documentation"
(sha1: 191891c0)

- compatible string is cdns,wdt-r1p2
- remove device_type property
- remove int reset property (reset-on-timeout is bool)
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Series-to: arm-soc
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Add pinctrl descriptions to the zc702 and zc706 device trees.
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Tested-by: NAndreas Färber <afaerber@suse.de>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Add USB nodes to zc702, zc706 and zed device trees.
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

The fact that all supported boards use the same 33MHz crystal is a
co-incidence. The Zynq PS support a range of crystal freqs so the
hardcoded setting should be removed from the dtsi. Re-implement it
on the board level.

This prepares support for Zynq boards with different crystal
frequencies (e.g. the Digilent ZYBO).
Acked-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NPeter Crosthwaite <crosthwaite.peter@gmail.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

sed -i 's/}\ ;/};/g'
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Add the cadence watchdog node to the Zynq devicetree.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Add missing reference for memory-controller.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Add missing reference for ADC node.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

By in sync with others node and add also baseaddr
to the node name.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Due to dependencies between timer and CPU frequency, only changes by
powers of two are allowed. The clocksource driver prevents other
changes, but with cpufreq and its governors it can result in being
spammed with error messages constantly. Hence, remove the 222 MHz OPP.
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

The size of the GEM's register area is only 0x1000 bytes.
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Add the DDR controller to the Zynq devicetree.
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Remove space before semicolon.
sed -i 's/}\ ;/};/g' arch/arm/boot/dts/zynq-*
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Move the GEM's size and address cells properties to the common
dtsi file.

Cc: Andreas Färber <afaerber@suse.de>
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Reviewed-by: NAndreas Färber <afaerber@suse.de>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Add node describing Zynq's CAN controller.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>

Signed-off-by: NAndreas Färber <afaerber@suse.de>
Reviewed-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Signed-off-by: NAndreas Färber <afaerber@suse.de>
Acked-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Add node describing Zynq's GPIO controller.
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Add node for the Xilinx A/D Converter.

Cc: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

The Zynq UART is Cadence IP and the driver has been renamed accordingly.
Migrate the DT to use the new binding for the UART driver.
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
Acked-by: NRob Herring <robh@kernel.org>
Tested-by: NMichal Simek <michal.simek@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Provide information through SOC_BUS to user space.
Silicon revision is provided through devcfg device.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

To silence the warning
	cpufreq_cpu0: failed to get cpu0 regulator: -19
from the cpufreq driver regarding a missing regulator,
add a fixed regulator to the DT.
Zynq does not support voltage scaling and the CPU rail should always be
supplied with 1 V, hence it is added in the SOC-level dtsi.
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

 - Use generic node names
 - Fix up some weird formatting and white spaces
 - Update copyright info
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>

This is likely a copy-and-paste error from the
ARM GIC documentation, that has already been fixed.

address-cells should have been set to 0, as with the size
cells. As having those properties set to 0 is the
same thing as not specifying them, drop them completely.
Signed-off-by: NLucas Stach <l.stach@pengutronix.de>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Tested-by: NMichal Simek <michal.simek@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Specify the 'clock-latency' property to avoid certain cpufreq governors
from refusing to work with the following error:
  ondemand governor failed, too long transition latency of HW, fallback to performance governor
Reported-by: NMike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Tested-by: NMike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

The generic cpufreq-cpu0 driver can scale the CPU frequency on Zynq
SOCs. Add the required platform device to the BSP and appropriate
OPPs to the dts.

Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: devicetree@vger.kernel.org
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: NMichal Simek <michal.simek@xilinx.com>

The clkc has its registers in the range of the slcr.
Instead of passing around the slcr base address pointer, let the clkc get the
address from the DT.
This prepares the slcr to be a real driver with multiple memory ranges
(slcr, clocks, pinctrl,...)
Signed-off-by: NSteffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Split the slcr into an early part for unlocking and cpu starting
and a later syscon driver.
Also add "syscon" compatible property for slcr.
Signed-off-by: NSteffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: NMichal Simek <michal.simek@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Add nodes for the Arasan SDHCI controller to Zynq dts files.
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Add a 'cpus' node to describe the CPU cores of Zynq.
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

The bindings for the TTC changed in commit 'arm: zynq: Use standard
timer binding' (e932900a). That change
removed possible subnodes from this driver rendering the 'clock-ranges'
property invalid for this node.
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
Acked-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

The zynq includes a Cadence GEM IP core. This is compatible with the macb driver.
Add it to the zynq-7000 DT.
Signed-off-by: NSteffen Trumtrar <s.trumtrar@pengutronix.de>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Josh Cartwright <josh.cartwright@ni.com>
[soren: rebased to current Linus tree, added zc706 + zed support, moved phy-mode property to board level dtses]
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Zynq is based on an ARM Cortex-A9 MPCore, which features the
arm_global_timer in its SCU. Therefore enable the timer for Zynq.
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: NMichal Simek <michal.simek@xilinx.com>

Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Set the default status for UARTs to disabled in the zynq-7000.dtsi file
and let board dts files enable the UARTs on demand.
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Reviewed-by: NSteffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Migrate the Zynq platform and its drivers to use the new clock
controller driver.
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Cc: John Stultz <john.stultz@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Jiri Slaby <jslaby@suse.cz>
Cc: linux-serial@vger.kernel.org
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Acked-by: NMike Turquette <mturquette@linaro.org>