1. 09 9月, 2016 2 次提交
    • M
      arm64: simplify sysreg manipulation · adf75899
      Mark Rutland 提交于
      A while back we added {read,write}_sysreg accessors to handle accesses
      to system registers, without the usual boilerplate asm volatile,
      temporary variable, etc.
      
      This patch makes use of these across arm64 to make code shorter and
      clearer. For sequences with a trailing ISB, the existing isb() macro is
      also used so that asm blocks can be removed entirely.
      
      A few uses of inline assembly for msr/mrs are left as-is. Those
      manipulating sp_el0 for the current thread_info value have special
      clobber requiremends.
      Signed-off-by: NMark Rutland <mark.rutland@arm.com>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      adf75899
    • M
      arm64: sysreg: allow write_sysreg to use XZR · 7aff4a2d
      Mark Rutland 提交于
      Currently write_sysreg has to allocate a temporary register to write
      zero to a system register, which is unfortunate given that the MSR
      instruction accepts XZR as an operand.
      
      Allow XZR to be used when appropriate by fiddling with the assembly
      constraints.
      
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
      Reviewed-by: NRobin Murphy <robin.murphy@arm.com>
      Signed-off-by: NMark Rutland <mark.rutland@arm.com>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      7aff4a2d
  2. 01 7月, 2016 1 次提交
    • A
      arm64: trap userspace "dc cvau" cache operation on errata-affected core · 7dd01aef
      Andre Przywara 提交于
      The ARM errata 819472, 826319, 827319 and 824069 for affected
      Cortex-A53 cores demand to promote "dc cvau" instructions to
      "dc civac". Since we allow userspace to also emit those instructions,
      we should make sure that "dc cvau" gets promoted there too.
      So lets grasp the nettle here and actually trap every userland cache
      maintenance instruction once we detect at least one affected core in
      the system.
      We then emulate the instruction by executing it on behalf of userland,
      promoting "dc cvau" to "dc civac" on the way and injecting access
      fault back into userspace.
      Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
      [catalin.marinas@arm.com: s/set_segfault/arm64_notify_segfault/]
      Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
      7dd01aef
  3. 28 4月, 2016 1 次提交
  4. 20 4月, 2016 1 次提交
  5. 13 4月, 2016 1 次提交
  6. 31 3月, 2016 1 次提交
  7. 19 2月, 2016 1 次提交
    • J
      arm64: kernel: Add support for User Access Override · 57f4959b
      James Morse 提交于
      'User Access Override' is a new ARMv8.2 feature which allows the
      unprivileged load and store instructions to be overridden to behave in
      the normal way.
      
      This patch converts {get,put}_user() and friends to use ldtr*/sttr*
      instructions - so that they can only access EL0 memory, then enables
      UAO when fs==KERNEL_DS so that these functions can access kernel memory.
      
      This allows user space's read/write permissions to be checked against the
      page tables, instead of testing addr<USER_DS, then using the kernel's
      read/write permissions.
      Signed-off-by: NJames Morse <james.morse@arm.com>
      [catalin.marinas@arm.com: move uao_thread_switch() above dsb()]
      Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
      57f4959b
  8. 18 2月, 2016 1 次提交
  9. 17 2月, 2016 1 次提交
  10. 14 12月, 2015 1 次提交
  11. 21 10月, 2015 2 次提交
    • S
      arm64: Keep track of CPU feature registers · 3c739b57
      Suzuki K. Poulose 提交于
      This patch adds an infrastructure to keep track of the CPU feature
      registers on the system. For each register, the infrastructure keeps
      track of the system wide safe value of the feature bits. Also, tracks
      the which fields of a register should be matched strictly across all
      the CPUs on the system for the SANITY check infrastructure.
      
      The feature bits are classified into following 3 types depending on
      the implication of the possible values. This information is used to
      decide the safe value for a feature.
      
      LOWER_SAFE  - The smaller value is safer
      HIGHER_SAFE - The bigger value is safer
      EXACT       - We can't decide between the two, so a predefined safe_value is used.
      
      This infrastructure will be later used to make better decisions for:
      
       - Kernel features (e.g, KVM, Debug)
       - SANITY Check
       - CPU capability
       - ELF HWCAP
       - Exposing CPU Feature register to userspace.
      Signed-off-by: NSuzuki K. Poulose <suzuki.poulose@arm.com>
      Tested-by: NDave Martin <Dave.Martin@arm.com>
      [catalin.marinas@arm.com: whitespace fix]
      Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
      3c739b57
    • S
      arm64: Move mixed endian support detection · cdcf817b
      Suzuki K. Poulose 提交于
      Move the mixed endian support detection code to cpufeature.c
      from cpuinfo.c. This also moves the update_cpu_features()
      used by mixed endian detection code, which will get more
      functionality.
      
      Also moves the ID register field shifts to asm/sysreg.h,
      where all the useful definitions will end up in later patches.
      Signed-off-by: NSuzuki K. Poulose <suzuki.poulose@arm.com>
      Tested-by: NDave Martin <Dave.Martin@arm.com>
      Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
      cdcf817b
  12. 20 10月, 2015 2 次提交
  13. 27 7月, 2015 3 次提交
  14. 25 7月, 2014 1 次提交