Export the default read/write oob functions (for the standard and syndrome
scheme), so that drivers can use them for their raw implementation and
implement their own functions for the normal oob operation.

This is required if your ECC engine is capable of fixing some of the OOB
data. In this case you have to overload the ->read_oob() and ->write_oob(),
but if you don't specify the ->read/write_oob_raw() functions they are
assigned to the ->read/write_oob() implementation, which is not what you
want.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

Adapt the NAND controller clk rate to the tWB, tADL, tWHR and tRHW
timings instead of returning an error when the maximum clk divisor is
not big enough to provide an appropriate timing.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

The ONFI spec says that EDO should be enabled if the host drives tRC less
than 30ns, but the code just tests for the tRC_min value extracted from
the timings exposed by the NAND chip not the timings actually configured
in the NAND controller.
Fix that by first rounding down the requested clk_rate with
clk_round_rate() and then checking if tRC is actually smaller than 30ns.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

Unlike what is specified in the Allwinner datasheets, the NAND clock rate
is not equal to 2/T but 1/T. Fix the clock rate selection accordingly.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

sunxi_nand_chip_set_timings() is extracting a pointer to the nfc from the
nand->controller field, but this field is initialized after
sunxi_nand_chip_set_timings() call.
Reorder the calls to avoid any problem.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

The core now takes care of parsing generic DT properties in
nand_scan_ident() when nand_set_flash_node() has been called.
Rely on this initialization instead of calling of_get_nand_xxx()
manually.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: NEzequiel Garcia <ezequiel@vanguardiasur.com.ar>

The core now takes care of parsing generic DT properties in
nand_scan_ident() when nand_set_flash_node() has been called.
Rely on this initialization instead of calling of_get_nand_xxx()
manually.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Tested-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Reviewed-by: NNicolas Ferre <nicolas.ferre@atmel.com>

It also contains some minor related changes:
1) Don't warn if kzalloc fails as it dumps stack on its own
2) Use %pR format for displaying whole resource to avoid invalid format
   warning
Signed-off-by: NRafał Miłecki <zajec5@gmail.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).
Signed-off-by: NRafał Miłecki <zajec5@gmail.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).
Signed-off-by: NRafał Miłecki <zajec5@gmail.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).
Signed-off-by: NRafał Miłecki <zajec5@gmail.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).
Signed-off-by: NRafał Miłecki <zajec5@gmail.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).
Signed-off-by: NRafał Miłecki <zajec5@gmail.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).
Signed-off-by: NRafał Miłecki <zajec5@gmail.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).
Signed-off-by: NRafał Miłecki <zajec5@gmail.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).
Signed-off-by: NRafał Miłecki <zajec5@gmail.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

The core now takes care of parsing generic DT properties in
nand_scan_ident() when nand_set_flash_node() has been called.
Rely on this initialization instead of calling of_get_nand_xxx()
manually.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: NBrian Norris <computersforpeace@gmail.com>

The core now takes care of parsing generic DT properties in
nand_scan_ident() when nand_set_flash_node() has been called.
Rely on this initialization instead of calling of_get_nand_xxx()
manually.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: NRoger Quadros <rogerq@ti.com>
Tested-by: NFranklin S Cooper Jr. <fcooper@ti.com>

Some drivers are including linux/of_mtd.h even if they don't use any of
the of_get_nand_xxx() helpers.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: NHarvey Hunt <harvey.hunt@imgtec.com>

If there is only one bit difference in the ECC, the function should
return 1.
The result of "diff0 & ~(1<<fls(diff0))" is equal to diff0, so the
function actually returns -1.
Signed-off-by: NZhaoxiu Zeng <zhaoxiu.zeng@gmail.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

The new IFC controller version 2.0 has a different memory map page.
Upto IFC 1.4 PAGE size is 4 KB and from IFC2.0 PAGE size is 64KB.
This patch segregates the IFC global and runtime registers to appropriate
PAGE sizes.
Signed-off-by: NJaiprakash Singh <b44839@freescale.com>
Signed-off-by: NRaghav Dogra <raghav@freescale.com>
Acked-by: NLi Yang <leoyang.li@nxp.com>
Signed-off-by: NRaghav Dogra <raghav.dogra@nxp.com>
Acked-by: NScott Wood <oss@buserror.net>
Acked-by: NBrian Norris <computersforpeace@gmail.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

There's no reason to BUG() when parameters are being
validated. Drivers can get things wrong, and it's much nicer
to just throw a noisy warn and fail gracefully, than calling
BUG() and throwing the whole system down the drain.
Signed-off-by: NEzequiel Garcia <ezequiel@vanguardiasur.com.ar>
Reviewed-by: NRichard Weinberger <richard@nod.at>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

fix the raw_buffer pointer double free issue found by coverify.

CID 18344 (#2 of 2): Double free (USE_AFTER_FREE)
3. double_free: Calling gpmi_alloc_dma_buffer frees pointer
this->raw_buffer which has already been freed
Signed-off-by: NHan Xu <han.xu@nxp.com>
Reviewed-by: NRichard Weinberger <richard@nod.at>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

Document and match the brcm,brcmnand-v6.2 compatible string, the controller has
a register layout identical to the v6.0 version and supports prefetch. Update the
command shift logic to account for v6.2 controller which are the first ones to
use a shift of 0 (6.1 used a shift of 24).
Signed-off-by: NKamal Dasu <kdasu.kdev@gmail.com>
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>
Acked-by: NRob Herring <robh@kernel.org>
Acked-by: NBrian Norris <computersforpeace@gmail.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

Standardize the NAND controller/NAND chip DT representation. Now, all new
NAND controller drivers should comply with this representation, even if
they are only supporting a single NAND chip.

Existing drivers can keep support for the old representation (where only
the NAND chip was described), but are encouraged to also support the new
one.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: NBrian Norris <computersforpeace@gmail.com>
Acked-by: NRob Herring <robh@kernel.org>

bch->dev is already assigned to &pdev->dev in the probe function.
Remove the duplicate assignment done in jz4780_bch_get().
Signed-off-by: NJorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: NAcked-by: Harvey Hunt <harvey.hunt@imgtec.com>

New atmel SoCs are able to fix bitflips in erased pages, but old ones
are still impacted by this problem. Use nand_check_erased_ecc_chunk() to
handle this case.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Reported-by: NHerve Codina <herve.CODINA@celad.com>
Reviewed-by: NHerve Codina <herve.CODINA@celad.com>
Tested-by: NHerve Codina <herve.CODINA@celad.com>

This follows recent work on switching to enum nand_ecc_algo and
deprecating NAND_ECC_SOFT_BCH.
Signed-off-by: NRafał Miłecki <zajec5@gmail.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

Use recently added of_get_nand_ecc_algo for that.
Signed-off-by: NRafał Miłecki <zajec5@gmail.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

NAND subsystem is being slightly reworked to store ECC details in
separated fields. In future we'll want to add support for more DT
properties as specifying every possible setup with a single
"nand-ecc-mode" is a pretty bad idea.
To allow this let's add a helper that will support something like
"nand-ecc-algo" in future. Right now we use it for keeping backward
compatibility.
Signed-off-by: NRafał Miłecki <zajec5@gmail.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

Our nand_ecc_modes_t is already a bit abused by value NAND_ECC_SOFT_BCH.
This enum should store ECC mode only and putting algorithm details there
is a bad idea. It would result in too many values impossible to support
in a sane way.

To solve this problem let's add a new enum. We'll have to modify all
drivers to set it properly but once it's done it'll be possible to drop
NAND_ECC_SOFT_BCH. That will result in a cleaner design and more
possibilities like setting ECC algorithm for hardware ECC mode.
Signed-off-by: NRafał Miłecki <zajec5@gmail.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

Merge branch 'mtd-nand-trigger' of git://git.kernel.org/pub/scm/linux/kernel/git/j.anaszewski/linux-leds into nand/next

Pull leds-trigger changes from Jacek Anaszewski.
Create a generic mtd led-trigger to replace the exisitng nand led-trigger
implementation.

* 'mtd-nand-trigger' of git://git.kernel.org/pub/scm/linux/kernel/git/j.anaszewski/linux-leds:
  mtd: Hook I/O activity to the MTD LED trigger
  mtd: nand: Remove the "nand-disk" LED trigger
  leds: trigger: Introduce a MTD (NAND/NOR) trigger
  mtd: Uninline mtd_write_oob and move it to mtdcore.c
  leds: trigger: Introduce a kernel panic LED trigger

Pull NAND/GPMC updates from Roger Quadros:
 "We do a couple of things in this series which result in cleaner device
  tree implementation, faster perfomance and multi-platform support. As
  an added bonus we get to use the GPMC_WAIT pins as GPI/Interrupts.

  - Establish a custom interface between NAND and GPMC driver. This is
    needed because all of the NAND registers sit in the GPMC register
    space.

  - Clean up device tree support so that omap-gpmc IP and the omap2 NAND
    driver can be used on non-OMAP platforms. e.g. Keystone.

  - Implement GPIOCHIP for the GPMC WAITPINS. SoCs can contain 2 to 4 of
    these and most of them would be unused otherwise. It also allows a
    cleaner implementation of NAND Ready pin status for the NAND driver.

  - Implement GPMC IRQ domain to proivde the 2 NAND events and GPMC
    WAITPIN edge interrupts.

  - Implement GPIOlib based NAND ready pin checking for OMAP NAND driver.
    On dra7-evm, Read speed increases from 13768 KiB/ to 17246 KiB/s.
    Write speed was unchanged at 7123 KiB/s."

* 'for-v4.7/gpmc-mtd-common' of github.com:rogerq/linux:
  mtd: nand: omap2: Implement NAND ready using gpiolib
  memory: omap-gpmc: Prevent GPMC_STATUS from being accessed via gpmc_regs
  memory: omap-gpmc: Support WAIT pin edge interrupts
  memory: omap-gpmc: Reserve WAITPIN if needed for WAIT monitoring
  memory: omap-gpmc: Support general purpose input for WAITPINs
  memory: omap-gpmc: Move device tree binding to correct location
  memory: omap-gpmc: Prevent mapping into 1st 16MB
  mtd: nand: omap: Update DT binding documentation
  mtd: nand: omap: Clean up device tree support
  mtd: nand: omap: Copy platform data parameters to omap_nand_info data
  mtd: nand: omap: Switch to using GPMC-NAND ops for writebuffer empty check
  mtd: nand: omap: Use gpmc_omap_get_nand_ops() to get NAND registers
  memory: omap-gpmc: Implement IRQ domain for NAND IRQs
  memory: omap-gpmc: Add GPMC-NAND ops to get writebufferempty status
  memory: omap-gpmc: Introduce GPMC to NAND interface
  ARM: OMAP2+: gpmc: Add gpmc timings and settings to platform data
  ARM: OMAP2+: gpmc: Add platform data

The GPMC WAIT pin status are now available over gpiolib.
Update the omap_dev_ready() function to use gpio instead of
directly accessing GPMC register space.
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Acked-by: NBrian Norris <computersforpeace@gmail.com>
Acked-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: NTony Lindgren <tony@atomide.com>

GPMC_STATUS register is private to the GPMC module and must not be
accessed directly by NAND driver through the gpmc_regs.

They must use gpmc_omap_get_nand_ops() instead.
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>

OMAPs can have 2 to 4 WAITPINs that can be used as edge triggered
interrupts if not used for memory wait state insertion.

Support these interrupts via the gpmc IRQ domain.

The gpmc IRQ domain interrupt map is:

0 - NAND_fifoevent
1 - NAND_termcount
2 - GPMC_WAIT0 edge
3 - GPMC_WAIT1 edge, and so on
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Acked-by: NRob Herring <robh@kernel.org>
Acked-by: NTony Lindgren <tony@atomide.com>

If the device attached to GPMC wants to use the WAIT pin
for WAIT monitoring then we reserve it internally for
exclusive use.
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>

OMAPs can have 2 to 4 WAITPINs that can be used as general purpose
input if not used for memory wait state insertion.

The first user will be the OMAP NAND chip to get the NAND
read/busy status using gpiolib.
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Acked-by: NRob Herring <robh@kernel.org>
Acked-by: NTony Lindgren <tony@atomide.com>

omap-gpmc.c is a memory controller so move the binding to the
right place.
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Acked-by: NRob Herring <robh@kernel.org>
Acked-by: NTony Lindgren <tony@atomide.com>

We have been preventing mapping GPMC children in the
first 1MB but really it has to be the first 16MB as
the minimum GPMC partition size is 16MB.

Also print an error message if CS mapping fails
due to DT requesting address outside the GPMC
map.
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>