- 23 1月, 2014 1 次提交
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由 Leonid Yegoshin 提交于
The Fixed Page Size TLB (FTLB) is a set-associative dual entry TLB. Its purpose is to reduce the number of TLB misses by increasing the effective TLB size and keep the implementation complexity to minimum levels. A supported core can have both VTLB and FTLB. Reviewed-by: NJames Hogan <james.hogan@imgtec.com> Reviewed-by: NPaul Burton <paul.burton@imgtec.com> Signed-off-by: NLeonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: NMarkos Chandras <markos.chandras@imgtec.com> Signed-off-by: NJohn Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6139/
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- 17 9月, 2013 1 次提交
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由 Ralf Baechle 提交于
boot_cpu_data is used the same as current_cpu_data but returns the CPU data for CPU 0. This means it doesn't have to use smp_processor_id() thus no need to disable preemption. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 01 2月, 2013 1 次提交
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由 Ralf Baechle 提交于
Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 19 1月, 2011 1 次提交
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由 David Daney 提交于
Probe c0_config4 for KScratch registers and report them in /proc/cpuinfo. Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1877/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 03 2月, 2010 1 次提交
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由 Guenter Roeck 提交于
Linux kernel 2.6.32 and later allocate address space from the top of the kernel virtual memory address space. This patch implements virtual memory size detection for 64 bit MIPS CPUs to avoid resulting crashes. Signed-off-by: NGuenter Roeck <guenter.roeck@ericsson.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/935/Reviewed-by: NDavid Daney <ddaney@caviumnetworks.com> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 08 6月, 2009 1 次提交
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由 Ralf Baechle 提交于
Outlining fixes the issue were on certain CPUs such as the R10000 family the delay loop would need an extra cycle if it overlaps a cacheline boundary. The rewrite also fixes build errors with GCC 4.4 which was changed in way incompatible with the kernel's inline assembly. Relying on pure C for computation of the delay value removes the need for explicit. The price we pay is a slight slowdown of the computation - to be fixed on another day. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 11 10月, 2008 2 次提交
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由 David Daney 提交于
This is the main support code for the patch. Here we just add the code, the following patches hook it up. Signed-off-by: NDavid Daney <ddaney@avtrex.com> Signed-off-by: NRalf Baechle <ralf@linux-mips.org> create mode 100644 arch/mips/include/asm/watch.h create mode 100644 arch/mips/kernel/watch.c
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由 Ralf Baechle 提交于
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 16 6月, 2008 1 次提交
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由 Chris Dearman 提交于
Signed-off-by: NChris Dearman <chris@mips.com> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 29 1月, 2008 1 次提交
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由 Ralf Baechle 提交于
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 16 11月, 2007 1 次提交
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由 Ralf Baechle 提交于
Shadow register support would not possibly have worked on multicore systems. The support code for it was also depending not on MIPS R2 but VSMP or SMTC kernels even though it makes perfect sense with UP kernels. SR sets are a scarce resource and the expected usage pattern is that users actually hardcode the register set numbers in their code. So fix the allocator by ditching it. Move the remaining CPU probe bits into the generic CPU probe. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 12 10月, 2007 2 次提交
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由 Ralf Baechle 提交于
So far /proc/cpuinfo has been the only user but human readable processor name are more useful than that for proc. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Ralf Baechle 提交于
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 17 3月, 2007 1 次提交
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由 Atsushi Nemoto 提交于
Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 30 11月, 2006 1 次提交
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由 Ralf Baechle 提交于
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 26 4月, 2006 1 次提交
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由 David Woodhouse 提交于
Signed-off-by: NDavid Woodhouse <dwmw2@infradead.org>
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- 19 4月, 2006 1 次提交
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由 Ralf Baechle 提交于
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 19 3月, 2006 1 次提交
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由 Atsushi Nemoto 提交于
If dcache_size != icache_size or dcache_size != scache_size, or set-associative cache, icache/scache does not flushed properly. Make blast_?cache_page_indexed() masks its index value correctly. Also, use physical address for physically indexed pcache/scache. Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 30 10月, 2005 1 次提交
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由 Ralf Baechle 提交于
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 17 4月, 2005 1 次提交
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由 Linus Torvalds 提交于
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
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