1. 14 12月, 2016 6 次提交
    • R
      platform/x86: intel_pmc_core: Add LTR IGNORE debug feature · 9c2ee199
      Rajneesh Bhardwaj 提交于
      SPT LTR_IGN register provides a means to make the PMC ignore the LTR values
      reported by the individual PCH devices.
      
      echo <IP Offset> > /sys/kernel/debug/pmc_core/ltr_ignore.
      
      When a particular IP Offset bit is set the PMC will ignore the LTR value
      reported by the corresponding IP when the PMC performs the latency
      coalescing.
      
      IP Offset	IP Name
      0		SPA
      1		SPB
      2		SATA
      3		GBE
      4		XHCI
      5		RSVD
      6		ME
      7		EVA
      8		SPC
      9		Azalia/ADSP
      10		RSVD
      11		LPSS
      12		SPD
      13		SPE
      14		Camera
      15		ESPI
      16		SCC
      17		ISH
      Signed-off-by: NRajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
      [dvhart: pmc_core_ltr_ignore_write local declaration order cleanup]
      Signed-off-by: NDarren Hart <dvhart@linux.intel.com>
      9c2ee199
    • R
      platform/x86: intel_pmc_core: Add MPHY PLL clock gating status · fe748227
      Rajneesh Bhardwaj 提交于
      ModPhy Common lanes can provide the clock gating status for the important
      system PLLs such as Gen2 USB3PCIE2 PLL, DMIPCIE3 PLL, SATA PLL and MIPI
      PLL.
      
      On SPT, in addition to the crystal oscillator clock, the 100Mhz Gen2
      USB3PCI2 PLL clock is used as the PLL reference clock and Gen2 PLL idling
      is a necessary condition for the platform to go into low power states like
      PC10 and S0ix.
      Signed-off-by: NRajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
      Signed-off-by: NDarren Hart <dvhart@linux.intel.com>
      fe748227
    • R
      platform/x86: intel_pmc_core: ModPhy core lanes pg status · 173943b3
      Rajneesh Bhardwaj 提交于
      The PCH implements a number of High Speed I/O (HSIO) lanes that are split
      between PCIe*, USB 3.0, SATA, GbE, USB OTG and SSIC. This patch shows the
      current power gating status of the available ModPhy Core lanes. This is
      done by sending a message to the PMC (MTPMC) that contains the XRAM
      register offset for the MPHY_CORE_STS_0 and MPHY_CORE_STS_1 and then by
      reading the response sent by the PMC (MFPMC).
      
      While enabling low power modes we often encounter situations when the
      ModPhy lanes are not power gated and it becomes hard to debug which lane is
      active and which is not in the absence of an external hardware debugger
      (JTAG/ITP). This patch eliminates the dependency on an external hardware
      debugger for reading the ModPhy Lanes power gating status.
      
      This patch requires PMC_READ_DISABLE setting to be disabled in the platform
      bios.
      
      cat /sys/kernel/debug/pmc_core/mphy_lanes_power_gating_status
      Signed-off-by: NRajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
      Signed-off-by: NDarren Hart <dvhart@linux.intel.com>
      173943b3
    • R
      platform/x86: intel_pmc_core: Add PCH IP Power Gating Status · 0bdfaf42
      Rajneesh Bhardwaj 提交于
      This patch adds the support for reading the power gating status of various
      devices present on Sunrise Point PCH. This is intended to be used for
      debugging purpose while tuning the platform for power optimizations and
      also to understand which devices (on PCH) are blocking the system to enter
      a low power state.
      
      Power Management Controller on Sunrise Point PCH provides access to "PGD
      PFET Enable Ack Status Registers (ppfear)". This patch reads and decodes
      this register and dumps the output in formatted manner showing various
      devices present on the PCH and their "Power Gating" status.
      
      Further documentation can be found in Intel 7th Gen Core family mobile u/y
      processor io datasheet volume 2.
      
      Sample output (stripped and not in order):
      
      cat /sys/kernel/debug/pmc_core/pch_ip_power_gating_status
      PMC				State: Not Power gated
      OPI-DMI				State: Not Power gated
      XHCI				State: Power gated
      LPSS				State: Power gated
      CSME_PSF			State: Not power gated
      Signed-off-by: NRajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
      Signed-off-by: NDarren Hart <dvhart@linux.intel.com>
      0bdfaf42
    • R
      platform/x86: intel_pmc_core: Fix PWRMBASE mask and mmio reg len · 8434709b
      Rajneesh Bhardwaj 提交于
      On Sunrise Point PCH, the Power Management Controller provides 4K bytes of
      memory space for various power management and debug registers. This fix is
      needed to access power management & debug registers that are mapped at a
      higher offset.
      
      Also, this provides a fix for correctly masking the PWRMBASE as the initial
      bits (0-11) are reserved.
      Signed-off-by: NRajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
      Signed-off-by: NDarren Hart <dvhart@linux.intel.com>
      8434709b
    • L
      platform/x86: acer-wmi: Only supports AMW0_GUID1 on acer family · 5241b193
      Lee, Chun-Yi 提交于
      The AMW0_GUID1 wmi is not only found on Acer family but also other
      machines like Lenovo, Fujitsu and Medion. In the past, acer-wmi handled
      those non-Acer machines by quirks list.
      
      But actually acer-wmi driver was loaded on any machine that had
      AMW0_GUID1. This behavior is strange because those machines should be
      supported by appropriate wmi drivers. e.g. fujitsu-laptop,
      ideapad-laptop.
      
      This patch adds the logic to check the machine that has AMW0_GUID1
      should be in Acer/Packard Bell/Gateway white list. But, it still keeps
      the quirk list of those supported non-acer machines for backward
      compatibility.
      Tested-by: NBjørn Mork <bjorn@mork.no>
      Signed-off-by: NLee, Chun-Yi <jlee@suse.com>
      Signed-off-by: NDarren Hart <dvhart@linux.intel.com>
      5241b193
  2. 23 10月, 2016 1 次提交
    • V
      platform/x86: Introduce support for Mellanox hotplug driver · 30488704
      Vadim Pasternak 提交于
      Enable system support for the Mellanox Technologies hotplug platform
      driver, which provides support for the next Mellanox basic systems:
      "msx6710", "msx6720", "msb7700", "msn2700", "msx1410", "msn2410",
      "msb7800", "msn2740", "msn2100" and also various number of derivative
      systems from the above basic types.
      This driver handles hot-plug events for the power suppliers, power
      cables and fans for the above systems.
      
      The Kconfig currently controlling compilation of this code is:
      driver/platform/x86:config MLX_CPLD_PLATFORM
                             tristate "Mellanox platform hotplug driver support"
      Signed-off-by: NVadim Pasternak <vadimp@mellanox.com>
      Signed-off-by: NDarren Hart <dvhart@linux.intel.com>
      30488704
  3. 20 10月, 2016 6 次提交
  4. 19 10月, 2016 22 次提交
  5. 18 10月, 2016 5 次提交
    • L
      Merge branch 'core-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip · 351267d9
      Linus Torvalds 提交于
      Pull misc fixes from Ingo Molnar:
       "A CPU hotplug debuggability fix and three objtool false positive
        warnings fixes for new GCC6 code generation patterns"
      
      * 'core-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
        cpu/hotplug: Use distinct name for cpu_hotplug.dep_map
        objtool: Skip all "unreachable instruction" warnings for gcov kernels
        objtool: Improve rare switch jump table pattern detection
        objtool: Support '-mtune=atom' stack frame setup instruction
      351267d9
    • L
      Merge tag 'firewire-update' of git://git.kernel.org/pub/scm/linux/kernel/git/ieee1394/linux1394 · 5aa43efe
      Linus Torvalds 提交于
      Pull firewire fixlet from Stefan Richter:
       "IEEE 1394 subsystem patch: catch an initialization error in the packet
        sniffer nosy"
      
      * tag 'firewire-update' of git://git.kernel.org/pub/scm/linux/kernel/git/ieee1394/linux1394:
        firewire: nosy: do not ignore errors in ioremap_nocache()
      5aa43efe
    • L
      Merge tag 'drm-fixes-for-v4.9-rc2' of git://people.freedesktop.org/~airlied/linux · 37c1e289
      Linus Torvalds 提交于
      Pull drm fixes from Dave Airlie:
       "Just had a couple of amdgpu fixes and one core fix I wanted to get out
        early to fix some regressions.
      
        I'm sure I'll have more stuff this week for -rc2"
      
      * tag 'drm-fixes-for-v4.9-rc2' of git://people.freedesktop.org/~airlied/linux: (22 commits)
        drm: Print device information again in debugfs
        drm/amd/powerplay: fix bug stop dpm can't work on Vi.
        drm/amd/powerplay: notify smu no display by default.
        drm/amdgpu/dpm: implement thermal sensor for CZ/ST
        drm/amdgpu/powerplay: implement thermal sensor for CZ/ST
        drm/amdgpu: disable smu hw first on tear down
        drm/amdgpu: fix amdgpu_need_full_reset (v2)
        drm/amdgpu/si_dpm: Limit clocks on HD86xx part
        drm/amd/powerplay: fix static checker warnings in smu7_hwmgr.c
        drm/amdgpu: potential NULL dereference in debugfs code
        drm/amd/powerplay: fix static checker warnings in smu7_hwmgr.c
        drm/amd/powerplay: fix static checker warnings in iceland_smc.c
        drm/radeon: change vblank_time's calculation method to reduce computational error.
        drm/amdgpu: change vblank_time's calculation method to reduce computational error.
        drm/amdgpu: clarify UVD/VCE special handling for CG
        drm/amd/amdgpu: enable clockgating only after late init
        drm/radeon: allow TA_CS_BC_BASE_ADDR on SI
        drm/amdgpu: initialize the context reset_counter in amdgpu_ctx_init
        drm/amdgpu/gfx8: fix CGCG_CGLS handling
        drm/radeon: fix modeset tear down code
        ...
      37c1e289
    • M
      pinctrl: intel: Only restore pins that are used by the driver · c538b943
      Mika Westerberg 提交于
      Dell XPS 13 (and maybe some others) uses a GPIO (CPU_GP_1) during suspend
      to explicitly disable USB touchscreen interrupt. This is done to prevent
      situation where the lid is closed the touchscreen is left functional.
      
      The pinctrl driver (wrongly) assumes it owns all pins which are owned by
      host and not locked down. It is perfectly fine for BIOS to use those pins
      as it is also considered as host in this context.
      
      What happens is that when the lid of Dell XPS 13 is closed, the BIOS
      configures CPU_GP_1 low disabling the touchscreen interrupt. During resume
      we restore all host owned pins to the known state which includes CPU_GP_1
      and this overwrites what the BIOS has programmed there causing the
      touchscreen to fail as no interrupts are reaching the CPU anymore.
      
      Fix this by restoring only those pins we know are explicitly requested by
      the kernel one way or other.
      
      Cc: stable@vger.kernel.org
      Link: https://bugzilla.kernel.org/show_bug.cgi?id=176361Reported-by: NAceLan Kao <acelan.kao@canonical.com>
      Tested-by: NAceLan Kao <acelan.kao@canonical.com>
      Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      c538b943
    • V
      pinctrl: baytrail: Fix lockdep · a171bc51
      Ville Syrjälä 提交于
      Initialize the spinlock before using it.
      
      INFO: trying to register non-static key.
      the code is fine but needs lockdep annotation.
      turning off the locking correctness validator.
      CPU: 2 PID: 1 Comm: swapper/0 Not tainted 4.8.0-dwc-bisect #4
      Hardware name: Intel Corp. VALLEYVIEW C0 PLATFORM/BYT-T FFD8, BIOS BLAKFF81.X64.0088.R10.1403240443 FFD8_X64_R_2014_13_1_00 03/24/2014
       0000000000000000 ffff8800788ff770 ffffffff8133d597 0000000000000000
       0000000000000000 ffff8800788ff7e0 ffffffff810cfb9e 0000000000000002
       ffff8800788ff7d0 ffffffff8205b600 0000000000000002 ffff8800788ff7f0
      Call Trace:
       [<ffffffff8133d597>] dump_stack+0x67/0x90
       [<ffffffff810cfb9e>] register_lock_class+0x52e/0x540
       [<ffffffff810d2081>] __lock_acquire+0x81/0x16b0
       [<ffffffff810cede1>] ? save_trace+0x41/0xd0
       [<ffffffff810d33b2>] ? __lock_acquire+0x13b2/0x16b0
       [<ffffffff810cf05a>] ? __lock_is_held+0x4a/0x70
       [<ffffffff810d3b1a>] lock_acquire+0xba/0x220
       [<ffffffff8136f1fe>] ? byt_gpio_get_direction+0x3e/0x80
       [<ffffffff81631567>] _raw_spin_lock_irqsave+0x47/0x60
       [<ffffffff8136f1fe>] ? byt_gpio_get_direction+0x3e/0x80
       [<ffffffff8136f1fe>] byt_gpio_get_direction+0x3e/0x80
       [<ffffffff813740a9>] gpiochip_add_data+0x319/0x7d0
       [<ffffffff81631723>] ? _raw_spin_unlock_irqrestore+0x43/0x70
       [<ffffffff8136fe3b>] byt_pinctrl_probe+0x2fb/0x620
       [<ffffffff8142fb0c>] platform_drv_probe+0x3c/0xa0
      ...
      
      Based on the diff it looks like the problem was introduced in
      commit 71e6ca61 ("pinctrl: baytrail: Register pin control handling")
      but I wasn't able to verify that empirically as the parent commit
      just oopsed when I tried to boot it.
      
      Cc: Cristina Ciocan <cristina.ciocan@intel.com>
      Cc: stable@vger.kernel.org
      Fixes: 71e6ca61 ("pinctrl: baytrail: Register pin control handling")
      Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Acked-by: NMika Westerberg <mika.westerberg@linux.intel.com>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      a171bc51