1. 10 11月, 2016 1 次提交
  2. 07 11月, 2016 1 次提交
    • P
      drm/i915/gvt: implement scratch page table tree for shadow PPGTT · 3b6411c2
      Ping Gao 提交于
      All the unused entries in the page table tree(PML4E->PDPE->PDE->PTE)
      should point to scratch page table/scratch page to avoid page walk error
      due to the page prefetching.
      When removing an entry in shadow PPGTT,  it need map to scratch page
      also, the older implementation use single scratch page to assign to all
      level entries, it doesn't align the page walk behavior when removed
      entry is in PML, PDP, PD.  To avoid potential page walk error this patch
      implement a scratch page tree to replace the single scratch page.
      
      v2: more details in commit message address Kevin's comments.
      Signed-off-by: NPing Gao <ping.a.gao@intel.com>
      Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      3b6411c2
  3. 25 10月, 2016 2 次提交
  4. 20 10月, 2016 5 次提交
  5. 14 10月, 2016 1 次提交
    • Z
      drm/i915/gvt: vGPU graphics memory virtualization · 2707e444
      Zhi Wang 提交于
      The vGPU graphics memory emulation framework is responsible for graphics
      memory table virtualization. Under virtualization environment, a VM will
      populate the page table entry with guest page frame number(GPFN/GFN), while
      HW needs a page table filled with MFN(Machine frame number). The
      relationship between GFN and MFN(Machine frame number) is managed by
      hypervisor, while GEN HW doesn't have such knowledge to translate a GFN.
      
      To solve this gap, shadow GGTT/PPGTT page table is introdcued.
      
      For GGTT, the GFN inside the guest GGTT page table entry will be translated
      into MFN and written into physical GTT MMIO registers when guest write
      virtual GTT MMIO registers.
      
      For PPGTT, a shadow PPGTT page table will be created and write-protected
      translated from guest PPGTT page table.  And the shadow page table root
      pointers will be written into the shadow context after a guest workload
      is shadowed.
      
      vGPU graphics memory emulation framework consists:
      
      - Per-GEN HW platform page table entry bits extract/de-extract routines.
      - GTT MMIO register emulation handlers, which will call hypercall to do
      GFN->MFN translation when guest write GTT MMIO register
      - PPGTT shadow page table routines, e.g. shadow create/destroy/out-of-sync
      Signed-off-by: NZhi Wang <zhi.a.wang@intel.com>
      Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      2707e444