The value of armclk_mask needs to be inverted for use as a mask on
the register value when updating ARM_RATIO.

This is critical for cpufreq support, without it attempts to scale
the frequency of the core trash pretty much the entire clock tree.
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: NBen Dooks <ben-linux@fluff.org>

If the requested clock is faster than the parent clock then the
parent clock is the closest we can get to the request so we need
to return that instead of the requested clock.
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: NBen Dooks <ben-linux@fluff.org>

In the s3c_gpiolib_getchip implementation for s3c24xx the check whether a pin is
in the gpio banks range is reversed. Thus the function returns NULL for valid
pins and the gpio chip if its not valid.

As a result gpio states are not saved/restored properly during suspend/resume.
Signed-off-by: NBen Dooks <ben-linux@fluff.org>

This functionality is needed to kmap_atomic() highmem pages that may
potentially have or are about to set up other mappings with
non-standard caching attributes.
Signed-off-by: NThomas Hellstrom <thellstrom@vmware.com>
Signed-off-by: NDave Airlie <airlied@redhat.com>

Those definitions are already provided by asm-generic
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
Acked-by: NPaul Mundt <lethal@linux-sh.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

mm: Pass virtual address to [__]p{te,ud,md}_free_tlb()

Upcoming paches to support the new 64-bit "BookE" powerpc architecture
will need to have the virtual address corresponding to PTE page when
freeing it, due to the way the HW table walker works.

Basically, the TLB can be loaded with "large" pages that cover the whole
virtual space (well, sort-of, half of it actually) represented by a PTE
page, and which contain an "indirect" bit indicating that this TLB entry
RPN points to an array of PTEs from which the TLB can then create direct
entries. Thus, in order to invalidate those when PTE pages are deleted,
we need the virtual address to pass to tlbilx or tlbivax instructions.

The old trick of sticking it somewhere in the PTE page struct page sucks
too much, the address is almost readily available in all call sites and
almost everybody implemets these as macros, so we may as well add the
argument everywhere. I added it to the pmd and pud variants for consistency.
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
Acked-by: David Howells <dhowells@redhat.com> [MN10300 & FRV]
Acked-by: NNick Piggin <npiggin@suse.de>
Acked-by: Martin Schwidefsky <schwidefsky@de.ibm.com> [s390]
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

Reviewed the Makefile on request by Michal and this is the resulting changes.

o Use ':=' for assignmnet so we do not re-evaluate for each use
o Use $(shell echo xxx) to remove ""
o Replaced CFLAGS_KERNEL with KBUILD_CFLAGS
  The settings are equally relevant for modules and the linked kernel
o Dropped LDFLAGS_BLOB - it is no longer used
o Refactored assignmnets to libs-y and core-y
o Use MMU for the MMU specific extension. "MMUEXT" was hurting my eyes
  and I did not wanted it spread to m68k
Signed-off-by: NSam Ravnborg <sam@ravnborg.org>
Signed-off-by: NMichal Simek <monstr@monstr.eu>

Signed-off-by: NMichal Simek <monstr@monstr.eu>

For example reiserfs use this relocation type.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

New reloc type R_MICROBLAZE_32_PCREL_LO requires a null handler (no work to do).

Remove legacy hack for broken linker pre gcc-4.1.1, that required us to extract
an offset from the code, add it to the addend, then rewrite the instruction.

Fixup the invalid reloc type error output.

Boot tested with the xilinx_emaclite ethernet driver.
Signed-off-by: NJohn Williams <john.williams@petalogix.com>
Signed-off-by: NMichal Simek <monstr@monstr.eu>

The ipc system call is now unused in microblaze,
as the system call table points directly to the
indidual system calls for IPC.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NMichal Simek <monstr@monstr.eu>

This patch add support for cases where load/store instruction
in put/get_user macro gets unaligned pointer to data and this
address is not valid. I prevent all cases which can failed.
I had to disable first stage of unaligned handler which is used
only for noMMU kernel and the whole work is done when interrupt
is enabled.
You have enable HW support for detect unaligned access in Microblaze.

This patch fixed three LTP tests:
getpeername01, getsockname01, socketpair01
Signed-off-by: NMichal Simek <monstr@monstr.eu>

Signed-off-by: NMichal Simek <monstr@monstr.eu>

Calling fixup when we are in kernel mode. This
prevent fault for copy_to/from_user. This fault
was find thanks to writev01/03/04 LTP tests.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

We need to define _PAGE_FILE macro and change pte
functions. Microblaze use the same MMU as PowerPC
that's why we define _PAGE_FILE in the same style.
This change fixed remap_file_pages01 LTP test.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

For 64bits arguments gcc caused that put_user macro
works with wrong value because of optimalization.
Adding volatile caused that gcc not optimized it.

It is possible to use (as Blackfin do) two put_user
macros with 32bits arguments but there is one more
instruction which is due to duplication zero return
value which is called put_user_asm macro.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

It is necessary to zeroed r7 when r7 points to bad
dtb - this caused that we have correct messages
about compiled-in dtb or passing via r7
Signed-off-by: NMichal Simek <monstr@monstr.eu>

I can't clear r7 because if I do it I lose information
where DTB come from.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

Print accurate message about place where FDT blob is.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

If r7 is zero at kernel boot, or does not point to a valid DTB, then
we fall back to a DTB (assumed to be) linked statically in the kernel, instead
of blindly copying bogus cruft into the kernel DTB memory region
Signed-off-by: NJohn Williams <john.williams@petalogix.com>
Signed-off-by: NMichal Simek <monstr@monstr.eu>

Remove duplicated #include('s) in
  arch/microblaze/include/asm/io.h
Signed-off-by: NHuang Weiyi <weiyi.huang@gmail.com>
Signed-off-by: NMichal Simek <monstr@monstr.eu>

This fix remove bug which we had till now in all
Microblaze MMU code. Primary tested on mmap01 LTP test.
We forget to flush invalid tlb which were changed - we
used them and there were wrong old data which wasn't correct.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

The combination of noexec=on and a clock_gettime call with clock id
CLOCK_THREAD_CPUTIME_ID is broken. The vdso code switches to the
access register mode to get access to the per-cpu data structure to
execute the magic ectg instruction. After the ectg instruction the
code always switches back to the primary mode but for noexec=on the
correct mode is the secondary mode. The effect of the bug is that the
user space program looses the access to all mappings without PROT_EXEC,
e.g. the stack. The problem is fixed by restoring the mode that has
been active before the switch to the access register mode.
Signed-off-by: NMartin Schwidefsky <schwidefsky@de.ibm.com>

vdso per cpu area allocation in smp_prepare_cpus() happens with GFP_KERNEL
but irqs disabled. Triggers this one:

Badness at kernel/lockdep.c:2280
Modules linked in:
CPU: 0 Not tainted 2.6.30 #2
Process swapper (pid: 1, task: 000000003fe88000, ksp: 000000003fe87eb8)
Krnl PSW : 0400c00180000000 0000000000083360 (lockdep_trace_alloc+0xec/0xf8)
[...]
Call Trace:
([<00000000000832b6>] lockdep_trace_alloc+0x42/0xf8)
 [<00000000000b1880>] __alloc_pages_internal+0x3e8/0x5c4
 [<00000000000b1b4a>] __get_free_pages+0x3a/0xb0
 [<0000000000026546>] vdso_alloc_per_cpu+0x6a/0x18c
 [<00000000005eff82>] smp_prepare_cpus+0x322/0x594
 [<00000000005e8232>] kernel_init+0x76/0x398
 [<000000000001bb1e>] kernel_thread_starter+0x6/0xc
 [<000000000001bb18>] kernel_thread_starter+0x0/0xc

Fix this by moving the allocation out of the irqs disabled section.
Reported-by: NChristian Borntraeger <borntraeger@de.ibm.com>
Signed-off-by: NHeiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: NMartin Schwidefsky <schwidefsky@de.ibm.com>

swsusp_arch_suspend() actually saves all cpu register contents on
hibernation.
Machine checks must be disabled since swsusp_arch_suspend() stores
register contents to their lowcore save areas. That's the same
place where register contents on machine checks would be saved.
To avoid register corruption disable machine checks.
We must also disable machine checks in the new psw mask for
program checks, since swsusp_arch_suspend() may generate program
checks.
Signed-off-by: NHeiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: NMartin Schwidefsky <schwidefsky@de.ibm.com>

Our swsusp_arch_suspend() backend implementation disables prefixing
by setting the contents of the prefix register to 0.
However afterwards common code functions are called which might
access percpu data structures.
Since the lowcore contains e.g. the percpu base pointer this isn't
a good idea. So fix this by copying the hibernating cpu's lowcore to
absolute address zero.
Signed-off-by: NHeiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: NMartin Schwidefsky <schwidefsky@de.ibm.com>

Timer interrupts are excluded from being disabled during suspend. The
clock events code manages the disabling of clock events on its own
because the timer interrupt needs to be functional before the resume
code reenables the device interrupts.

The mfgpt timer request its interrupt without setting the IRQF_TIMER
flag so suspend_device_irqs() disables it as well which results in a
fatal resume failure.

Adding IRQF_TIMER to the interupt flags when requesting the mrgpt
timer interrupt solves the problem.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
LKML-Reference: <new-submission>
Cc: Andres Salomon <dilinger@debian.org>
Cc: stable@kernel.org

If we've logically disabled apics, don't probe the PCI space for the
AMD extended APIC ID.

[ Impact: prevent boot crash under Xen. ]
Signed-off-by: NJeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com>
Reported-by: NBastian Blank <bastian@waldi.eu.org>
Signed-off-by: NH. Peter Anvin <hpa@zytor.com>

Fix a gcc unused variables warning.
Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>

CONFIG_X86_THRESHOLD used in arch/x86/kernel/irqinit.c is always
undefined.  Rename it to the correct name "CONFIG_X86_MCE_THRESHOLD".
Signed-off-by: NHidehiro Kawai <hidehiro.kawai.ez@hitachi.com>
Reviewed-by: NHidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
Cc: Andi Kleen <andi@firstfloor.org>
LKML-Reference: <4A667FD4.3010509@hitachi.com>
Signed-off-by: NH. Peter Anvin <hpa@zytor.com>

Need to clear both nodes and nodes_add state for start/end.
Signed-off-by: NAndi Kleen <ak@linux.intel.com>
LKML-Reference: <20090718065657.GA2898@basil.fritz.box>
Signed-off-by: NH. Peter Anvin <hpa@zytor.com>
Cc: stable@kernel.org

Fix the condition checking the result of strchr() (which previously
could result in an oops), and make the function return the number of
bytes actively used.

[ Impact: fix oops ]
Signed-off-by: NJan Beulich <jbeulich@novell.com>
Cc: Andi Kleen <andi@firstfloor.org>
LKML-Reference: <4A5F04B7020000780000AB59@vpn.id2.novell.com>
Signed-off-by: NH. Peter Anvin <hpa@zytor.com>

The movq instruction, generated by __put_user_asm() when used for
64-bit data, takes a sign-extended immediate ("e") not a zero-extended
immediate ("Z").
Signed-off-by: NH. Peter Anvin <hpa@zytor.com>
Cc: Uros Bizjak <ubizjak@gmail.com>
Cc: stable@kernel.org

arch/x86/include/asm/uaccess_64.h uses wrong asm operand constraint
("ir") for movq insn. Since movq sign-extends its immediate operand,
"er" constraint should be used instead.

Attached patch changes all uses of __put_user_asm in uaccess_64.h to use
"er" when "q" insn suffix is involved.

Patch was compile tested on x86_64 with defconfig.
Signed-off-by: NUros Bizjak <ubizjak@gmail.com>
Signed-off-by: NH. Peter Anvin <hpa@zytor.com>
Cc: stable@kernel.org

The CompuLab SBC-fitPC2 board needs to reboot via BIOS.
Signed-off-by: NDenis Turischev <denis@compulab.co.il>
Signed-off-by: NMike Rapoport <mike@compulab.co.il>
Signed-off-by: NH. Peter Anvin <hpa@zytor.com>

The Blackfin serial headers were inverting the CTS value leading to wrong
handling of the CTS line which broke CTS/RTS handling completely.
Signed-off-by: NSonic Zhang <sonic.zhang@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>
Signed-off-by: NAlan Cox <alan@linux.intel.com>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

Fix i2c_board_info definitions - we were defining the 'type' field
of these structures twice since the first argument of I2C_BOARD_INFO
sets this field.  Move the second definition into I2C_BOARD_INFO().
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
Acked-by: NJean Delvare <khali@linux-fr.org>
Acked-by: NBen Dooks <ben-linux@fluff.org>

The .data.read_mostly and .data.cacheline_aligned sections
aren't covered by the _sdata .. _edata range on x86-64. This
affects kmemleak reporting leading to possible false
positives by not scanning the whole data section.
Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
Tested-by: NAlexey Fisher <bug-track@fisher-privat.net>
Acked-by: NSam Ravnborg <sam@ravnborg.org>
Cc: Pekka Enberg <penberg@cs.helsinki.fi>
LKML-Reference: <1247565175.28240.37.camel@pc1117.cambridge.arm.com>
Signed-off-by: NIngo Molnar <mingo@elte.hu>
Cc: Sam Ravnborg <sam@ravnborg.org>

AMI BIOS with low memory corruption was found on Intel DG45ID
board (Bug 13710). Add this board to the blacklist - in the
(somewhat optimistic) hope of future boards/BIOSes from Intel
not having this bug.

Also see:

  http://bugzilla.kernel.org/show_bug.cgi?id=13736Signed-off-by: NAlexey Fisher <bug-track@fisher-privat.net>
Cc: ykzhao <yakui.zhao@intel.com>
Cc: alan@lxorguk.ukuu.org.uk
Cc: <stable@kernel.org>
LKML-Reference: <1247660169-4503-1-git-send-email-bug-track@fisher-privat.net>
Signed-off-by: NIngo Molnar <mingo@elte.hu>

The BSS section macros in vmlinux.lds.h currently place the .sbss
input section outside the bounds of [__bss_start, __bss_end].  On all
architectures except for microblaze that handle both .sbss and
__bss_start/__bss_end, this is wrong: the .sbss input section is
within the range [__bss_start, __bss_end].  Relatedly, the example
code at the top of the file actually has __bss_start/__bss_end defined
twice; I believe the right fix here is to define them in the
BSS_SECTION macro but not in the BSS macro.

Another problem with the current macros is that several
architectures have an ALIGN(4) or some other small number just before
__bss_stop in their linker scripts.  The BSS_SECTION macro currently
hardcodes this to 4; while it should really be an argument.  It also
ignores its sbss_align argument; fix that.

mn10300 is the only user at present of any of the macros touched by
this patch.  It looks like mn10300 actually was incorrectly converted
to use the new BSS() macro (the alignment of 4 prior to conversion was
a __bss_stop alignment, but the argument to the BSS macro is a start
alignment).  So fix this as well.

I'd like acks from Sam and David on this one.  Also CCing Paul, since
he has a patch from me which will need to be updated to use
BSS_SECTION(0, PAGE_SIZE, 4) once this gets merged.
Signed-off-by: NTim Abbott <tabbott@ksplice.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: David Howells <dhowells@redhat.com>
Signed-off-by: NSam Ravnborg <sam@ravnborg.org>