Move all DISPC register definitions to a new header dispc.h. There are
separate register offset definitions for GFX, VID1 and VID2 pipeline share
register definitions by using an argument. The introduction of VID3 pipeline
on OMAP4 will not let us use the above method since VID3 pipe register offsets
don't map with VID1 and VID2 offsets.

Represent overlay registers as DISPC_OVL_XXXX(plane), where the plane argument
tells the overlay. Register offsets are calculated as:

DISPC_OVL_XXXX(plane) = DISPC_OVL_BASE(plane) + DISPC_XXXX_OFFSET(plane)

Idea suggested by Tomi Valkeinen.
Signed-off-by: NArchit Taneja <archit@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

Change enum dss_clk_source to omap_dss_clock_source and move it to
'plat/display.h'. Change the enum members to attach "OMAP_" in the beginning.
These changes are done in order to specify the clock sources for DSS in the
board file.
Signed-off-by: NArchit Taneja <archit@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

arch/arm/plat-omap/include/plat/display.h is an include for the OMAP DSS
driver. A more logical place for it is in include/video.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

Adding function to reset/set gamma table bit for TV interface, currently
only support for disabled is added.
Signed-off-by: NMythri P K <mythripk@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

On OMAP3, the pixel clock for the LCD manager was derived through DISPC_FCLK as:

Lcd Pixel clock = DISPC_FCLK / lcd / pcd

Where lcd and pcd are divisors in the DISPC_DIVISOR register.

On OMAP4, the pixel clocks for LCD1 and LCD2 managers are derived from 2 new
clocks named LCD1_CLK and LCD2_CLK. The pixel clocks are calculated as:

Lcd_o Pixel clock = LCDo_CLK / lcdo /pcdo, o = 1, 2

Where lcdo and pcdo registers are divisors in DISPC_DIVISORo registers.

LCD1_CLK and LCD2_CLK can have DSS_FCLK, and the M4 divider clocks of DSI1 PLL
and DSI2 PLL as clock sources respectively. Introduce functions to select and
get the clock source for these new clocks. Modify DISPC functions get the
correct lck and pck rates based on the clock source of these clocks. Since
OMAP2/3 don't have these clocks, force OMAP2/3 to always have the LCD_CLK source
as DSS_CLK_SRC_FCK by introducing a dss feature.

Introduce clock source names for OMAP4 and some register field changes in
DSS_CTRL on OMAP4.

Currently, LCD2_CLK can only have DSS_FCLK as its clock source as DSI2 PLL
functionality hasn't been introduced yet. BUG for now if DSI2 PLL is selected as
clock.
Signed-off-by: NArchit Taneja <archit@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

Clean up some of the DSS functions which select/get clock sources, use switch
to select the clock source members since more clock sources will be introduced
later on.

Remove the use of macro CONFIG_OMAP2_DSS_DSI in dispc_fclk_rate, use a dummy
inline for function for dsi_get_pll_hsdiv_dispc_rate() instead for code clarity.
Signed-off-by: NArchit Taneja <archit@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

Fix handling of error in omap_dispc_register_isr() in case there are no
free isr slots available.
Reported-by: NBen Tucker <btucker@mpcdata.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

Using dss_features to select independent core clock divider and setting
it. Added the register used, to DISPC context save and restore group

-----------------------------------------------------------------------
In OMAP4, the minimum DISPC_CORE_CLK required can be expressed as:

	DISPC_CORE_CLK >= max(PCLK1*HSCALE1, PCLK2*HSCALE2, ...)

Where PCLKi is the pixel clock generated by MANAGERi and HSCALEi is the
maximum horizontal downscaling done through MANAGERi

Based on the usecase, core clk can be increased or decreased at runtime
to save power. Such mechanism are not yet implemented. Hence, we set the
core clock divisor to 1, to support maximum range of resolutions
------------------------------------------------------------------------
Signed-off-by: NRaghuveer Murthy <raghuveer.murthy@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

The OMAP4 DISPC_DIVISOR1 is backward compatible to OMAP3xxx DISPC_DIVISOR.
However DISPC_DIVISOR is also provided in OMAP4, to control DISPC_CORE_CLK
independent of Primary and Secondary display clocks.

Renamed DISPC_DIVISOR(ch) to DISPC_DIVISORo(ch), to facilitate introduction
of DISPC_DIVISOR register, which is specific for OMAP4. OMAP4 has 3 registers
DISPC_DIVISOR, DISPC_DIVISOR1 and DISPC_DIVISOR2.

Also updated, all the usages of DISPC_DIVISOR(ch) to DISPC_DIVISORo(ch).
Use DISPC_DIVISORo(ch) when DISPC_DIVISOR1 or DISPC_DIVISOR2 has to be
configured

OMAP4 TRM uses DISPC_DIVISORo generically to refer to DISPC_DIVISOR1 and
DISPC_DIVISOR2
Signed-off-by: NRaghuveer Murthy <raghuveer.murthy@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

DSI PLL output clock names have been made more generic. The clock name
describes what the source of the clock and what clock is used for. Some of
DSI PLL parameters like dividers and DSI PLL source have also been made more
generic.

dsi1_pll_fclk and dsi2_pll_fclk have been changed as dsi_pll_hsdiv_dispc_clk
and dsi_pll_hsdiv_dsi_clk respectively. Also, the hsdividers are now named
regm_dispc and regm_dsi instead of regm3 and regm4.

Functions and macros named on the basis of these clock names have also been
made generic.
Signed-off-by: NArchit Taneja <archit@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

Clock source names vary across OMAP2/3 and OMAP4, the clock source enum
names have been made generic in the driver, but for purposes of debugging
and dumping clock sources, it is better to preserve the actual TRM name of
the clock.

Introduce a dss feature function 'dss_feat_get_clk_source_name()' which
returns a string with the TRM clock name for the current OMAP in use. The OMAP
specific name is printed along the generic name within brackets.
Signed-off-by: NArchit Taneja <archit@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

The enum members of 'dss_clk_source' have clock source names specific to
OMAP2/3. Change the names to more generic terms such that they now describe
where the clocks come from and what they are used for.

Also, change the enum member names to have "DSS_CLK_SRC" instead of "DSS_SRC"
for more clarity.
Signed-off-by: NArchit Taneja <archit@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

Add dss_features and register fields to incorporate changes in DISPC pipelines
between OMAP3 and OMAP4.

Register fields added: FEAT_REG_HORIZONTALACCU, FEAT_REG_VERTICALACCU
DSS Features added: FEAT_LINEBUFFERSPLIT, FEAT_ROWREPEATENABLE, FEAT_RESIZECONF

_dispc_set_scaling() and _dispc_set_rotation_attrs() have been cleaned up.
Signed-off-by: NArchit Taneja <archit@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

Currently, the core DSS platform device requests for an irq line for OMAP2 and
OMAP3. Make DISPC and DSI platform devices request for a shared IRQ line.

On OMAP3, the logical OR of DSI and DISPC interrupt lines goes to the MPU. There
is a register DSS_IRQSTATUS which tells if the interrupt came from DISPC or DSI.

On OMAP2, there is no DSI, only DISPC interrupts goto the MPU. There is no
DSS_IRQSTATUS register.

Hence, it makes more sense to have separate irq handlers corresponding to the
DSS sub modules instead of having a common handler.

Since on OMAP3 the logical OR of the lines goes to MPU, the irq line is shared
among the IRQ handlers.

The hwmod irq info has been removed for DSS to DISPC and DSI for OMAP2 and OMAP3
hwmod databases. The Probes of DISPC and DSI now request for irq handlers.
Signed-off-by: NArchit Taneja <archit@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

enum dss_clock structure is replaced with generic names that
could be used across OMAP2420, 2430, 3xxx, 44xx platforms.
Signed-off-by: NSumit Semwal <sumit.semwal@ti.com>
Signed-off-by: NArchit Taneja <archit@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

DSS, DISPC, DSI, RFBI, VENC baseaddr can be obtained from platform_get_resource().
This API in turn picks the right silicon baseaddr from the hwmod database.
So hardcoding of base addr could be removed.
Reviewed-by: NPaul Walmsley <paul@pwsan.com>
Reviewed-by: NKevin Hilman <khilman@ti.com>
Tested-by: NKevin Hilman <khilman@ti.com>
Signed-off-by: NSumit Semwal <sumit.semwal@ti.com>
Signed-off-by: NSenthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

This patch replaces printk's in the init/probe functions to dev_dbg
for boot time optimization.
Reviewed-by: NKevin Hilman <khilman@ti.com>
Tested-by: NKevin Hilman <khilman@ti.com>
Signed-off-by: NSumit Semwal <sumit.semwal@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

Hwmod adaptation design requires each of the DSS HW IP to be a platform driver.
So a platform_driver for DISPC is created and init exit methods are moved from core.c
to its driver probe,remove. pdev member has to be maintained by its own drivers.

DISPC platform driver is registered from inside omap_dss_probe, in the order desired.
Signed-off-by: NSenthilvadivu Guruswamy <svadivu@ti.com>
Signed-off-by: NSumit Semwal <sumit.semwal@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

A panel connects to one of the overlay managers of DSS through some interface block.
On OMAP4, specifying the type of the display is not sufficient to conclude which manager
the panel should be connected to.
Hence, a new member 'channel' is introduced in omap_dss_device structure to determine
which manager the panel uses. The dss_recheck_connections() called in dss_driver_probe()
uses this channel parameter to set the correct manager to the corresponding omap_dss_device.

The channel parameter is used only once to ensure the correct managers are set for each
panel. The parameter dssdev->manager->id will take care of ensuring that the panel and
then the interface driver configures the correct DISPC channel.

Also, add a new Overlay Manager in manager.c, make other changes needed for LCD2 channel.
Signed-off-by: NSumit Semwal <sumit.semwal@ti.com>
Signed-off-by: NMukund Mittal <mmittal@ti.com>
Signed-off-by: NSamreen <samreen@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@nokia.com>

DISPC_CONFIG bits LCDENABLEPOL, LCDENABLESIGNAL, PCKFREEENABLE and FUNCGATED
have been removed from OMAP4, use dss_features to handle them correctly.
Signed-off-by: NArchit Taneja <archit@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@nokia.com>

DISPC functions are modified in order to work when the manager is LCD2.
This includes:
Adding new IRQs specific to LCD2 and their handling.
Provide dumps of the new manager's registers.
Provide dumps of the new manager's clocks.
Checks for channel for registers DISPC_CONTROL2 and DISPC_CONFIG2
which can't be parametrized.
Signed-off-by: NSumit Semwal <sumit.semwal@ti.com>
Signed-off-by: NMukund Mittal <mmittal@ti.com>
Signed-off-by: NSamreen <samreen@ti.com>
Signed-off-by: NArchit Taneja <archit@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@nokia.com>

The following dispc functions are also changed to incorporate channel as an argument:
	-dispc_lclk_rate()
	-dispc_pclk_rate()
	-dispc_set_pol_freq()
	-dispc_set_clock_div()
	-dispc_get_clock_div()
Signed-off-by: NSumit Semwal <sumit.semwal@ti.com>
Signed-off-by: NMukund Mittal <mmittal@ti.com>
Signed-off-by: NSamreen <samreen@ti.com>
Signed-off-by: NArchit Taneja <archit@ti.com>
[tomi.valkeinen@nokia.com: fixed trivial compile error]
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@nokia.com>

The interface drivers (dsi.c, sdi.c etc) need to call dispc functions with
dssdev->manager->id as a parameter to specify the DISPC channel which they want
to configure/use, this is required as the same functions are now used to configure
dispc registers of different channels.

The following dispc functions are changed to incorporate channel as an argument:
	-dispc_enable_fifohandcheck()
	-dispc_set_lcd_size()
	-dispc_set_parallel_interface_mode()
	-dispc_set_tft_data_lines()
	-dispc_set_lcd_display_type()
	-dispc_set_lcd_timings()
Signed-off-by: NSumit Semwal <sumit.semwal@ti.com>
Signed-off-by: NMukund Mittal <mmittal@ti.com>
Signed-off-by: NSamreen <samreen@ti.com>
Signed-off-by: NArchit Taneja <archit@ti.com>
[tomi.valkeinen@nokia.com: fixed trivial compile error]
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@nokia.com>

On OMAP4, we have a new DISPC channel for Overlay Manager LCD2. There is a set
of regsiters for LCD2 channel similar to the existing LCD channel, like
DISPC_CONTROL2, DISPC_DIVISOR2, DISPC_CONFIG2 and so on.

Introduce new enum members for LCD2 Channel and corresponding Overlay Manager
in display.h.

Represent the following DISPC register defines with channel as a parameter
to differentiate between LCD and LCD2 registers (and also DIGIT in some cases):

DISPC_DEFAULT_COLOR, DISPC_TRANS_COLOR, DISPC_TIMING_H, DISPC_TIMING_V,
DISPC_POL_FREQ, DISPC_DIVISOR, DISPC_SIZE_LCD, DISPC_DATA_CYCLEk,
DISPC_CPR_COEF_R, DISPC_CPR_COEF_G and DISPC_CPR_COEF_B

This parametrization helps in reducing the number of register defines for DISPC.
Replace the existing reads/writes to these registers in this new way.
Also, Introduce defines for registers DISPC_CONTROL2 and DISPC_CONFIG2 which
are used exclusively for LCD2 channel.
Signed-off-by: NSumit Semwal <sumit.semwal@ti.com>
Signed-off-by: NMukund Mittal <mmittal@ti.com>
Signed-off-by: NSamreen <samreen@ti.com>
Signed-off-by: NArchit Taneja <archit@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@nokia.com>

The supported set of color modes varies for different DISPC pipelines(plane)
and omap version. This makes the checks for validation of a color mode more
complicated as new omap versions are added.

A dss_feature function is created which tells if a color_mode is supported
for a plane on the current omap revision.
Signed-off-by: NArchit Taneja <archit@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@nokia.com>

Enable dss to process color formats with pre-mulitplied alpha.
With this we can have alpha values defined for each pixel
and hence can have different blending values for each pixel.
sysfs entry has been created for this and pre-multiplied alpha
support is turned off by default.
Signed-off-by: NSudeep Basavaraj <sudeep.basavaraj@ti.com>
Signed-off-by: NRajkumar N <rajkumar.nagarajan@ti.com>
Signed-off-by: NSamreen <samreen@ti.com>
Signed-off-by: NArchit Taneja <archit@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@nokia.com>

Read correct DISPC_CONFIG bit when the channel is DIGIT, remove extra line
at the end of the function.
Signed-off-by: NArchit Taneja <archit@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@nokia.com>

Calls init functions of dss_features during dss_probe, and the following
features are made omapxxxx independent:
  - number of managers, overlays
  - supported color modes for each overlay
  - supported displays for each manager
  - global aplha, and restriction of global alpha for video1 pipeline
  - The register field ranges : FIRHINC, FIRVINC, FIFOHIGHTHRESHOLD
    FIFOLOWTHRESHOLD and FIFOSIZE
Signed-off-by: NArchit Taneja <archit@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@nokia.com>

Reorganize scaler FIR filter data as FIR value tables from raw
register values. This makes them easier to understand and simplifies
register programming code.

No functional changes.
Signed-off-by: NGrazvydas Ignotas <notasas@gmail.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@nokia.com>

Previously a work was started on FRAMEDONE interrupt, and this work
either sent a BTA synchronously or looped until TE_SIZE was zero, to
wait for the end of the transfer.

This patch changes a BTA to be sent asynchronously from FRAMEDONE
interrupt, and when a BTA interrupt is received, the transfer is
finished. This way we do the whole process asynchronously, and also
inside interrupt context.

This will give us much better latency to handle the end of the frame
than with the previous work based solution.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@nokia.com>

When DSS transitions from off mode to on VENC may generate a spurious
SYNC_LOST_DIGIT error. Just ack it when restoring the context. Also
restore IRQENABLE last to avoid triggering interrupts before the
context is fully restored.
Signed-off-by: NVille Syrjälä <ville.syrjala@nokia.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@nokia.com>

Move enable/disable/suspend/resume from omap_dss_device to
omap_dss_driver.

This is part of a larger patch-set, which moves the control from omapdss
driver to the display driver.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@nokia.com>

Move enable/disable_channel() from omap_dss_device to overlay manager.

This is part of a larger patch-set, which moves the control from omapdss
driver to the display driver.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@nokia.com>

After changing the selection of DSI and DISPC clock source the users of
get_dsi/dispc_clk_source() functions were left unchanged.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@nokia.com>

Fix compilation of the CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS feature.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@nokia.com>

If the scaling ratio is below 0.5 video output width can't be identical
to the display width. Reject such settings.
Signed-off-by: NVille Syrjälä <ville.syrjala@nokia.com>
Acked-by: NTomi Valkeinen <tomi.valkeinen@nokia.com>

Collect interrupt statistics, printable via debugfs:

debugfs/omapdss/dispc_irq
debugfs/omapdss/dsi_irq

The counters are reset when printed.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@nokia.com>

This file implements DISPC (display controller) block of the OMAP DSS.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@nokia.com>