1. 05 10月, 2015 1 次提交
  2. 05 8月, 2015 1 次提交
  3. 24 7月, 2015 3 次提交
    • C
      tty/serial: at91: use 32bit writes into TX FIFO when DMA is enabled · 5f258b3e
      Cyrille Pitchen 提交于
      For now this improvement is only used with TX DMA transfers. The data
      width must be set properly when configuring the DMA controller. Also
      the FIFO configuration must be set to match the DMA transfer data
      width:
      TXRDYM (Transmitter Ready Mode) and RXRDYM (Receiver Ready Mode) must
      be set into the FIFO Mode Register. These values are used by the
      USART to trigger the DMA controller. In single data mode they are not
      used and should be reset to 0.
      So the TXRDYM bits are changed to FOUR_DATA; then USART triggers the
      DMA controller when at least 4 data can be written into the TX FIFO
      througth the THR. On the other hand the RXRDYM bits are left unchanged
      to ONE_DATA.
      
      Atmel eXtended DMA controller allows us to set a different data width
      for each part of a scatter-gather transfer. So when calling
      dmaengine_slave_config() to configure the TX path, we just need to set
      dst_addr_width to the maximum data width. Then DMA writes into THR are
      split into up to two parts. The first part carries the first data to
      be sent and has a length equal to the greatest multiple of 4 (bytes)
      lower than or equal to the total length of the TX DMA transfer. The
      second part carries the trailing data (up to 3 bytes). The first part
      is written by the DMA into THR using 32 bit accesses, whereas 8bit
      accesses are used for the second part.
      Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>
      Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      5f258b3e
    • C
      tty/serial: at91: add support to FIFOs · b5199d46
      Cyrille Pitchen 提交于
      Depending on the hardware, TX and RX FIFOs may be available. The RX
      FIFO can avoid receive overruns, especially when DMA transfers are
      not used to read data from the Receive Holding Register. For heavy
      system load, The CPU is likely not be able to fetch data fast enough
      from the RHR.
      
      In addition, the RX FIFO can supersede the DMA/PDC to control the RTS
      line when the Hardware Handshaking mode is enabled. Two thresholds
      are to be set for that purpose:
      - When the number of data in the RX FIFO crosses and becomes lower
        than or equal to the low threshold, the RTS line is set to low
        level: the remote peer is requested to send data.
      - When the number of data in the RX FIFO crosses and becomes greater
        than or equal to the high threshold, the RTS line is set to high
        level: the remote peer should stop sending new data.
      - low threshold <= high threshold
      Once these two thresholds are set properly, this new feature is
      enabled by setting the FIFO RTS Control bit of the FIFO Mode Register.
      
      FIFOs also introduce a new multiple data mode: the USART works either
      in multiple data mode or in single data (legacy) mode.
      
      If MODE9 bit is set into the Mode Register or if USMODE is set to
      either LIN_MASTER, LIN_SLAVE or LON_MODE, FIFOs operate in single
      data mode. Otherwise, they operate in multiple data mode.
      
      In this new multiple data mode, accesses to the Receive Holding
      Register or Transmit Holding Register slightly change.
      
      Since this driver implements neither the 9bit data feature (MODE9 bit
      set into the Mode Register) nor LIN modes, the USART works in
      multiple data mode whenever FIFOs are available and enabled. We also
      assume that data are 8bit wide.
      
      In single data mode, 32bit access CAN be used to read a single data
      from RHR or write a single data into THR.
      However in multiple data mode, a 32bit access to RHR now allows us to
      read four consecutive data from RX FIFO. Also a 32bit access to THR
      now allows to write four consecutive data into TX FIFO. So we MUST
      use 8bit access whenever only one data have to be read/written at a
      time.
      Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      b5199d46
    • C
      tty/serial: at91: remove bunch of macros to access UART registers · 4e7decda
      Cyrille Pitchen 提交于
      This patch replaces the UART_PUT_*, resp. UART_GET_*, macros by
      atmel_uart_writel(), resp. atmel_uart_readl(), inline function calls.
      Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      4e7decda
  4. 25 5月, 2015 1 次提交
  5. 07 5月, 2015 1 次提交
  6. 28 4月, 2015 1 次提交
  7. 07 3月, 2015 6 次提交
  8. 06 3月, 2015 1 次提交
  9. 10 1月, 2015 5 次提交
  10. 07 11月, 2014 7 次提交
  11. 06 11月, 2014 1 次提交
    • P
      serial: Refactor uart_flush_buffer() from uart_close() · 479e9b94
      Peter Hurley 提交于
      In the context of the final tty & port close, flushing the tx
      ring buffer after the hardware has already been shutdown and
      the ring buffer freed is neither required nor desirable.
      
      uart_flush_buffer() performs 3 operations:
      1. Resets tx ring buffer indices, but the tx ring buffer has
         already been freed and the indices are reset if the port is
         re-opened.
      2. Calls uart driver's flush_buffer() method
         5 in-tree uart drivers define flush_buffer() methods:
           amba-pl011, atmel-serial, imx, serial-tegra, timbuart
         These have been refactored into the shutdown() method, if
         required.
      3. Kicks the ldisc for more writing, but this is undesirable.
         The file handle is being released; any waiting writer will
         will be kicked out by tty_release() with a warning. Further,
         the N_TTY ldisc may generate SIGIO for a file handle which
         is no longer valid.
      
      Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
      Cc: Russell King <linux@arm.linux.org.uk>
      Cc: Laxman Dewangan <ldewangan@nvidia.com>
      Signed-off-by: NPeter Hurley <peter@hurleysoftware.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      479e9b94
  12. 20 10月, 2014 1 次提交
  13. 16 10月, 2014 1 次提交
  14. 09 9月, 2014 1 次提交
  15. 23 7月, 2014 1 次提交
  16. 20 6月, 2014 1 次提交
    • P
      serial: Fix IGNBRK handling · ef8b9ddc
      Peter Hurley 提交于
      If IGNBRK is set without either BRKINT or PARMRK set, some uart
      drivers send a 0x00 byte for BREAK without the TTYBREAK flag to the
      line discipline, when it should send either nothing or the TTYBREAK flag
      set. This happens because the read_status_mask masks out the BI
      condition, which uart_insert_char() then interprets as a normal 0x00 byte.
      
      SUS v3 is clear regarding the meaning of IGNBRK; Section 11.2.2, General
      Terminal Interface - Input Modes, states:
        "If IGNBRK is set, a break condition detected on input shall be ignored;
         that is, not put on the input queue and therefore not read by any
         process."
      
      Fix read_status_mask to include the BI bit if IGNBRK is set; the
      lsr status retains the BI bit if a BREAK is recv'd, which is
      subsequently ignored in uart_insert_char() when masked with the
      ignore_status_mask.
      
      Affected drivers:
      8250 - all
      serial_txx9
      mfd
      amba-pl010
      amba-pl011
      atmel_serial
      bfin_uart
      dz
      ip22zilog
      max310x
      mxs-auart
      netx-serial
      pnx8xxx_uart
      pxa
      sb1250-duart
      sccnxp
      serial_ks8695
      sirfsoc_uart
      st-asc
      vr41xx_siu
      zs
      sunzilog
      fsl_lpuart
      sunsab
      ucc_uart
      bcm63xx_uart
      sunsu
      efm32-uart
      pmac_zilog
      mpsc
      msm_serial
      m32r_sio
      
      Unaffected drivers:
      omap-serial
      rp2
      sa1100
      imx
      icom
      
      Annotated for fixes:
      altera_uart
      mcf
      
      Drivers without break detection:
      21285
      xilinx-uartps
      altera_jtaguart
      apbuart
      arc-uart
      clps711x
      max3100
      uartlite
      msm_serial_hs
      nwpserial
      lantiq
      vt8500_serial
      
      Unknown:
      samsung
      mpc52xx_uart
      bfin_sport_uart
      cpm_uart/core
      
      Fixes: Bugzilla #71651, '8250_core.c incorrectly handles IGNBRK flag'
      Reported-by: NIvan <athlon_@mail.ru>
      Signed-off-by: NPeter Hurley <peter@hurleysoftware.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      ef8b9ddc
  17. 29 5月, 2014 2 次提交
  18. 01 3月, 2014 2 次提交
  19. 14 2月, 2014 1 次提交
  20. 14 1月, 2014 1 次提交
    • M
      tty/serial: at91: disable uart timer at start of shutdown · 8bc661bf
      Marek Roszko 提交于
      The uart timer will schedule a tasklet when it fires. It is possible that it
      can fire inside _shutdown before it is killed in the dma and pdc cleanup
      routines. This causes a tasklet that exists after the port is shutdown, so when
      the kernel finally executes it, it panics as the tty port is NULL.
      
      This is a somewhat rare condition but its possible if a program keeps on
      opening/closing the port. It has been observed in particular with systemd
      boot messages that were causing a kernel panic because of this behavior.
      
      Moving the timer deletion to the beginning of the function stops a tasklet from
      being scheduled unexpectedly.
      Signed-off-by: NMarek Roszko <mark.roszko@gmail.com>
      Cc: stable <stable@vger.kernel.org> # v3.12
      [nicolas.ferre@atmel.com: modify commit message, call setup_timer() in any case]
      Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      8bc661bf
  21. 08 1月, 2014 1 次提交