The APQ8064 multimedia clock controller is fairly similar to the
8960 multimedia clock controller, except that gfx2d0/1 has been
removed and the gfx3d frequency is slightly faster when using the
newly introduced PLL15. We also add vcap clocks and a couple new
TV clocks.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add a driver for the global clock controller found on IPQ8064 based
platforms. This should allow most non-multimedia device drivers to probe
and control their clocks.

This is currently missing clocks for USB HSIC and networking devices.
Signed-off-by: NKumar Gala <galak@codeaurora.org>
Signed-off-by: NAndy Gross <agross@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add support for the multimedia clock controller found on the APQ8084
based platforms. This will allow the multimedia device drivers to
control their clocks.
Signed-off-by: NGeorgi Djakov <gdjakov@mm-sol.com>
[sboyd: Rework parent mapping to avoid conflicts]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add the clock tree definition for the new rk3288 SoC.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Acked-By: NMax Schwarz <max.schwarz@online.de>
Tested-By: NMax Schwarz <max.schwarz@online.de>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This adds a clock driver that handles the specific muxes, dividers and gates
of rk3188 and rk3066 SoCs.

The structure of the clock list resembles the arrangement of their
counterparts in the clock architecture diagrams found in the SoC
documentation.

Clocks exported to the clock provider are currently limited to well known
or measured ones. So additional clock exports may be necessary in the future.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Acked-By: NMax Schwarz <max.schwarz@online.de>
Tested-By: NMax Schwarz <max.schwarz@online.de>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Add the necessary clocks for SATA, PCIe and UFS to the
APQ8084 global clock controller (GCC). This will allow
the above device drivers to control their clocks.
Signed-off-by: NGeorgi Djakov <gdjakov@mm-sol.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This patch adds support for the global clock controller found on
the APQ8084 based devices. This includes UART, I2C, SPI etc.
Signed-off-by: NGeorgi Djakov <gdjakov@mm-sol.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add in the handful of new clocks and introduce a new reset table
with the few new resets.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The "aclk66_peric" clock is a gate clock with a whole bunch of gates
underneath it.  This big gate isn't very useful to include in our
clock tree.  If any of the children need to be turned on then the big
gate will need to be on anyway.  ...and there are plenty of other "big
gates" that aren't described in our clock tree, some of which shut off
collections of clocks that have no relationship in the hierarchy so
are hard to model.

"aclk66_peric" is causing earlyprintk problems since it gets disabled
as part of the boot process, so let's just remove it.

Strangely (and for no good reason) this clock is exported as part of
the common clock bindings.  Remove it since there are no in-kernel
device trees using it and no reason anyone out of tree should refer to
it either.
Signed-off-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

This patch fixes two problems: -

1) The device tree isn't currently providing sti-ethclk which is
required by the dwmac glue code to correctly configure the ethernet
PHY clock speed.

This means depending on what the bootloader/jtag has
configured this clock to, and what switch/hub the board is plugged
into you most likely will NOT successfully negotiate a ethernet link.

2) The stmmaceth clock was associated with the wrong clock. It was
referencing the PHY clock rather than the interconnect clock which
clocks the IP.

This patch also brings us closer to not having to boot the upstream
kernel with the clk_ignore_unused parameter.
Acked-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NPeter Griffin <peter.griffin@linaro.org>
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>

There's a enet clock gate missing in clock tree, thus add it.
Signed-off-by: NFugang Duan <B38611@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

The EXYNOS5410 clocks are statically listed and registered
using the Samsung specific common clock helper functions.
Signed-off-by: NTarek Dakhran <t.dakhran@samsung.com>
Signed-off-by: NVyacheslav Tyrtov <v.tyrtov@samsung.com>
Reviewed-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

A new PLL (gpll4) is added on msm8974 PRO devices to support a
faster sdc1 clock rate. Add support for this and the two new sdcc
cal clocks.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Add macros usable by device tree sources to reference r8a7779 clocks by
index.

Based on work for the r8a7791 SoC by Laurent Pinchart.
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This patch adds the missing sysmmu clocks for Display and
ISP blocks.
Signed-off-by: NCho KyongHo <pullip.cho@samsung.com>
Signed-off-by: NShaik Ameer Basha <shaik.ameer@samsung.com>
Acked-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

The AXM55xx family consists of devices that may contain up to 16 ARM Cortex-A15
cores (in a 4x4 cluster configuration). The cores within each cluster share an
L2 cache, and the clusters are connected to each other via a CCN-504 cache
coherent interconnect.

This machine requires CONFIG_ARM_LPAE enabled as all peripherals are located
above 4GB in the memory map.
Signed-off-by: NAnders Berg <anders.berg@lsi.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Currently the Tegra1x4 clock init code hard-codes the mux setting
for xusb_hs_src and treats it as a fixed-factor clock.  It is,
however, a mux which can be parented by either xusb_ss_src/2 or
pll_u_60M.  Add the fixed-factor clock xusb_ss_div2 and put an
entry in periph_clks[] for the xusb_hs_src mux.
Signed-off-by: NAndrew Bresticker <abrestic@chromium.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Patch adds DT entries for clockgen A0/1/10/11/12
Signed-off-by: NPankaj Dev <pankaj.dev@st.com>
Signed-off-by: NGabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>

Patch adds DT entries for clockgen A0/1/10/11/12
Signed-off-by: NPankaj Dev <pankaj.dev@st.com>
Signed-off-by: NGabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>

This adds a dt-binding include for Marvell Berlin BG2/BG2CD and BG2Q
core clock IDs.
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>

Exynos5800 clock structure is mostly similar to 5420 with only
a small delta changes. So the 5420 clock file is re-used for
5800 also. The common clocks for both are seggreagated and few
clocks which are different for both are separately initialized.
Signed-off-by: NAlim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: NArun Kumar K <arun.kk@samsung.com>
Acked-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Add clock driver for i.MX6 SoloX SoC.
Signed-off-by: NAnson Huang <b20788@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

This patch add new the clock drvier of Exynos3250 SoC based on Cortex-A7
using common clock framework. The CMU (Clock Management Unit) of Exynos3250
control PLLs(Phase Locked Loops) and generate system clocks for CPU, buses,
and function clocks for individual IPs.

The CMU of Exynos3250 includes following clock doamins:
- CPU block for Cortex-A7 MPCore processor
- LEFTBUS/RIGHTBUS block
- TOP block for G3D/MFC/LCD0/ISP/CAM/FSYS/MFC/PERIL/PERIR
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: NHyunhee Kim <hyunhee.kim@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: NInki Dae <inki.dae@samsung.com>
Signed-off-by: NSeung-Woo Kim <sw0312.kim@samsung.com>
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NKarol Wrona <k.wrona@samsung.com>
Signed-off-by: NYoungJun Cho <yj44.cho@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>

This patch adds some missing miscellaneous clocks specific
to exynos5420.
Signed-off-by: NRahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: NShaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

This patch adds the missing MAU block specific clocks.
Signed-off-by: NRahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: NShaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

This patch fixes some parent-child relationships according
to the latest datasheet and adds more clocks related to
PERIS and GEN blocks.
Signed-off-by: NRahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: NShaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

This patch includes,
    1] renaming of the HSI2C clocks
    2] renaming of spi clocks according to the datasheet
    3] fixes for child-parent relationships
    4] adding of more clocks related to PERIC block
    5] use GATE_IP_* offsets instead of GATE_BUS_*
Signed-off-by: NRahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: NShaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

This patch corrects some child-parent clock relationships,
and updates the clocks according to the latest datasheet.
Signed-off-by: NRahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: NShaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

This patch adds missing clocks of G2D block. It also removes
the aclkg3d alias from G3D block clocks.
Signed-off-by: NRahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: NShaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

This patch adds the missing GSCL and MSCL block clocks
and corrects some wrong parent-child relationships.
Signed-off-by: NRahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: NShaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

This patch adds minimum set of clocks to gate ISP block for
power saving.
Signed-off-by: NRahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: NShaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

Adds IDs for the clocks needed by the ARM Mali GPU
in exynos5420.
Signed-off-by: NArun Kumar K <arun.kk@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

Export sclk_hdmiphy clock to be usable from DT.
Signed-off-by: NTomasz Stanislawski <t.stanislaws@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

This patch adds the required clocks for ARM Mali IP
in Exynos5250.
Signed-off-by: NArun Kumar K <arun.kk@samsung.com>
[t.figa: Changed clock ID to avoid conflict with CLK_SSS]
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

Exynos4210 and Exynos4x12 SoCs have the PL330 MDMA IP block clock
defined exactly in same way in documentation. Using different
names for these clocks is a bit misleading. Since there is no users
of CLK_MDMA2 in existing dts files this patch drops CLK_MDMA2 and
replaces it with CLK_MDMA in the driver. This ensures PL330 MDMA
has correct clock assigned on Exynos4x12 SoCs.
Suggested-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

This patch adds gating clock for SSS(Security SubSystem)
module on Exynos5250/5420.
Signed-off-by: NNaveen Krishna Chatradhi <ch.naveen@samsung.com>
[t.figa: Fixed sort order and group name.]
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

Add macros which are used as Clock IDs in DT and clock file.
It also adds the documentation for the exynos5260 clocks.
Signed-off-by: NRahul Sharma <Rahul.Sharma@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: NMagnus Damm <damm+renesas@opensource.se>
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: NGeert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: NMagnus Damm <damm+renesas@opensource.se>
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Only essential clocks are added for now. Other clocks will be added when
needed.
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: NMagnus Damm <damm+renesas@opensource.se>
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>