- 19 10月, 2015 37 次提交
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由 Laurent Pinchart 提交于
The property name should be "gpio", not "gpios". Fix it. Signed-off-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: NSascha Hauer <s.hauer@pengutronix.de> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Michael Opdenacker 提交于
Fix a typo, replacing "pinctrl-name" by "pinctrl-names" in the Phytec phyFLEX-i.MX6 Quad dtsi. Also fix a typo in the board name Signed-off-by: NMichael Opdenacker <michael.opdenacker@free-electrons.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Shengjiu Wang 提交于
The correct core clock of spdif is SPDIF_GCLK, which is added to clock tree. So the dts also need to be updated. Signed-off-by: NShengjiu Wang <shengjiu.wang@freescale.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Stefan Agner 提交于
Enable NAND access by adding pinmux and NAND flash controller node to device tree. The NAND chips currently used on the Colibri VF61 requires 8-bit ECC per 512 byte page, hence specify 32-bit ECC strength per 2k page size. Reviewed-by: NBrian Norris <computersforpeace@gmail.com> Signed-off-by: NStefan Agner <stefan@agner.ch> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Stefan Agner 提交于
This adds the NAND flash controller (NFC) peripherial. The driver supports the SLC NAND chips found on Freescale's Vybrid Tower System Module. The Micron NAND chip on the module needs 4-bit ECC per 512 byte page. Use 24-bit ECC per 2k page, which is supported by the driver. Signed-off-by: NBill Pringlemeir <bpringlemeir@nbsps.com> Reviewed-by: NBrian Norris <computersforpeace@gmail.com> Signed-off-by: NStefan Agner <stefan@agner.ch> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Gary Bisson 提交于
Based on an i.MX6 Solo with 512MB DDR3. http://boundarydevices.com/product/nitrogen6_lite/Signed-off-by: NGary Bisson <gary.bisson@boundarydevices.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Gary Bisson 提交于
Based on i.MX6 Quad with 4GB of DDR3. http://boundarydevices.com/product/nitrogen6max/Signed-off-by: NGary Bisson <gary.bisson@boundarydevices.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Gary Bisson 提交于
Signed-off-by: NGary Bisson <gary.bisson@boundarydevices.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Gary Bisson 提交于
Signed-off-by: NGary Bisson <gary.bisson@boundarydevices.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Gary Bisson 提交于
Signed-off-by: NGary Bisson <gary.bisson@boundarydevices.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Gary Bisson 提交于
Signed-off-by: NGary Bisson <gary.bisson@boundarydevices.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Gary Bisson 提交于
Signed-off-by: NGary Bisson <gary.bisson@boundarydevices.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Gary Bisson 提交于
This patch adds the different touchscreens that can be connected using the displays available for this board. http://boundarydevices.com/product-category/displays/Signed-off-by: NGary Bisson <gary.bisson@boundarydevices.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Gary Bisson 提交于
This patch adds support for the 7" LCD display available for Sabrelite: http://boundarydevices.com/product/7-800x480-display/ Also add label to backlight_lcd and connect it to the panel. Signed-off-by: NGary Bisson <gary.bisson@boundarydevices.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Gary Bisson 提交于
This patch adds support for the 7" LCD display available for Nitrogen6x: http://boundarydevices.com/product/7-800x480-display/ Also add label to backlight_lcd and connect it to the panel. Signed-off-by: NGary Bisson <gary.bisson@boundarydevices.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Sanchayan Maity 提交于
Add device tree node for touchscreen support on Colibri VF50. The touchscreen functionality on VF50 uses the ADC channels of Vybrid and some GPIOs. Also add pinctrl nodes for proper pinmux. Signed-off-by: NSanchayan Maity <maitysanchayan@gmail.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Vladimir Zapolskiy 提交于
The change corrects cpu compatible property to a defined one, see Documentation/devicetree/bindings/arm/cpus.txt Signed-off-by: NVladimir Zapolskiy <vz@mleia.com> Cc: Sascha Hauer <kernel@pengutronix.de> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Vladimir Zapolskiy 提交于
The change corrects cpu compatible property to a defined one, see Documentation/devicetree/bindings/arm/cpus.txt Signed-off-by: NVladimir Zapolskiy <vz@mleia.com> Cc: Sascha Hauer <kernel@pengutronix.de> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Adrian Alonso 提交于
Add device tree node to support iomuxc-lpsr controller, fsl,input-sel phandle allows to get input select register base address which is shared from main iomuxc controller. Signed-off-by: NAdrian Alonso <aalonso@freescale.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Fugang Duan 提交于
Enable fec1 and fec2 for i.MX7d-sdb board. Signed-off-by: NFugang Duan <B38611@freescale.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Adrian Alonso 提交于
- Add imx7 SoC GPIO1 pad iomuxc settings <mux_reg conf_reg input_reg mux_mode input_val> - Fix UART input select daisy chain setting values Signed-off-by: NAdrian Alonso <aalonso@freescale.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Yuan Yao 提交于
The INA220 monitors both shunt drop and supply voltage. Signed-off-by: NYuan Yao <yao.yuan@freescale.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Alison Wang 提交于
This patch adds dma-coherent property for eTSEC nodes, so coherent DMA operations are supported. Signed-off-by: NAlison Wang <alison.wang@freescale.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Fabio Estevam 提交于
Add support for USBOTG1 and USBOTG2. Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com> Acked-by: NPeter Chen <peter.chen@freescale.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Fabio Estevam 提交于
Add USB OTG and Host support. Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com> Acked-by: NPeter Chen <peter.chen@freescale.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Fugang Duan 提交于
Add fec1 and fec2 nodes for i.MX7d soc. Signed-off-by: NFugang Duan <B38611@freescale.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Horia Geantă 提交于
Signed-off-by: NHoria Geantă <horia.geanta@freescale.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Haibo Chen 提交于
Add touch screen surpport for i.MX6UL-EVK board. Signed-off-by: NHaibo Chen <haibo.chen@freescale.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Haibo Chen 提交于
Add imx6ul touchscreen controller support. TSC module need ADC2 module to measure the touchscreen coordinate value. This patch put TSC and ADC2 together, make ADC2 module only be used for TSC, can't be used as a normal ADC. Signed-off-by: NHaibo Chen <haibo.chen@freescale.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Fabio Estevam 提交于
Add the PWM1-4 nodes. Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Fabio Estevam 提交于
The DCP block present on MX6SL is compatible with the one on MX28, so add the compatible string and also complete the interrupt entries. Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Rafał Miłecki 提交于
Starting with commit 8947e396 ("Documentation: dt: mtd: replace "nor-jedec" binding with "jedec, spi-nor"") we have "jedec,spi-nor" binding indicating support for JEDEC identification. Use it for all flashes that are supposed to support READ ID op according to the datasheets. Signed-off-by: NRafał Miłecki <zajec5@gmail.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Stefan Wahren 提交于
This patch enables On Chip OTP support for i.MX23 and i.MX28 SoCs, but keeps the old compatible string. Signed-off-by: NStefan Wahren <stefan.wahren@i2se.com> Reviewed-by: NFabio Estevam <fabio.estevam@freescale.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Haibo Chen 提交于
imx7d-sdb board has a eMMC5.0 on usdhc3. This eMMC support HS400. This patch add usdhc3 support for HS400 Signed-off-by: NHaibo Chen <haibo.chen@freescale.com> Acked-by: NDong Aisheng <aisheng.dong@freescale.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Anson Huang 提交于
i.MX6UL can be powered off by programming SNVS. When long press ON/OFF button(5 seconds), PMIC_ON_REQ pin will be set to low and external PMIC will be powered off. And system can be powered on by long press ON/OFF button again. Signed-off-by: NAnson Huang <b20788@freescale.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Anson Huang 提交于
Add MMDC support for i.MX6UL. Signed-off-by: NAnson Huang <b20788@freescale.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Anson Huang 提交于
Add SRAM support for i.MX6UL, it has 128KB ocram starting from 0x900000. Signed-off-by: NAnson Huang <b20788@freescale.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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- 12 9月, 2015 2 次提交
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由 Vineet Gupta 提交于
Newer bitfiles needs the reduced clk even for SMP builds Cc: <stable@vger.kernel.org> #4.2 Signed-off-by: NVineet Gupta <vgupta@synopsys.com> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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由 Mathieu Desnoyers 提交于
Here is an implementation of a new system call, sys_membarrier(), which executes a memory barrier on all threads running on the system. It is implemented by calling synchronize_sched(). It can be used to distribute the cost of user-space memory barriers asymmetrically by transforming pairs of memory barriers into pairs consisting of sys_membarrier() and a compiler barrier. For synchronization primitives that distinguish between read-side and write-side (e.g. userspace RCU [1], rwlocks), the read-side can be accelerated significantly by moving the bulk of the memory barrier overhead to the write-side. The existing applications of which I am aware that would be improved by this system call are as follows: * Through Userspace RCU library (http://urcu.so) - DNS server (Knot DNS) https://www.knot-dns.cz/ - Network sniffer (http://netsniff-ng.org/) - Distributed object storage (https://sheepdog.github.io/sheepdog/) - User-space tracing (http://lttng.org) - Network storage system (https://www.gluster.org/) - Virtual routers (https://events.linuxfoundation.org/sites/events/files/slides/DPDK_RCU_0MQ.pdf) - Financial software (https://lkml.org/lkml/2015/3/23/189) Those projects use RCU in userspace to increase read-side speed and scalability compared to locking. Especially in the case of RCU used by libraries, sys_membarrier can speed up the read-side by moving the bulk of the memory barrier cost to synchronize_rcu(). * Direct users of sys_membarrier - core dotnet garbage collector (https://github.com/dotnet/coreclr/issues/198) Microsoft core dotnet GC developers are planning to use the mprotect() side-effect of issuing memory barriers through IPIs as a way to implement Windows FlushProcessWriteBuffers() on Linux. They are referring to sys_membarrier in their github thread, specifically stating that sys_membarrier() is what they are looking for. To explain the benefit of this scheme, let's introduce two example threads: Thread A (non-frequent, e.g. executing liburcu synchronize_rcu()) Thread B (frequent, e.g. executing liburcu rcu_read_lock()/rcu_read_unlock()) In a scheme where all smp_mb() in thread A are ordering memory accesses with respect to smp_mb() present in Thread B, we can change each smp_mb() within Thread A into calls to sys_membarrier() and each smp_mb() within Thread B into compiler barriers "barrier()". Before the change, we had, for each smp_mb() pairs: Thread A Thread B previous mem accesses previous mem accesses smp_mb() smp_mb() following mem accesses following mem accesses After the change, these pairs become: Thread A Thread B prev mem accesses prev mem accesses sys_membarrier() barrier() follow mem accesses follow mem accesses As we can see, there are two possible scenarios: either Thread B memory accesses do not happen concurrently with Thread A accesses (1), or they do (2). 1) Non-concurrent Thread A vs Thread B accesses: Thread A Thread B prev mem accesses sys_membarrier() follow mem accesses prev mem accesses barrier() follow mem accesses In this case, thread B accesses will be weakly ordered. This is OK, because at that point, thread A is not particularly interested in ordering them with respect to its own accesses. 2) Concurrent Thread A vs Thread B accesses Thread A Thread B prev mem accesses prev mem accesses sys_membarrier() barrier() follow mem accesses follow mem accesses In this case, thread B accesses, which are ensured to be in program order thanks to the compiler barrier, will be "upgraded" to full smp_mb() by synchronize_sched(). * Benchmarks On Intel Xeon E5405 (8 cores) (one thread is calling sys_membarrier, the other 7 threads are busy looping) 1000 non-expedited sys_membarrier calls in 33s =3D 33 milliseconds/call. * User-space user of this system call: Userspace RCU library Both the signal-based and the sys_membarrier userspace RCU schemes permit us to remove the memory barrier from the userspace RCU rcu_read_lock() and rcu_read_unlock() primitives, thus significantly accelerating them. These memory barriers are replaced by compiler barriers on the read-side, and all matching memory barriers on the write-side are turned into an invocation of a memory barrier on all active threads in the process. By letting the kernel perform this synchronization rather than dumbly sending a signal to every process threads (as we currently do), we diminish the number of unnecessary wake ups and only issue the memory barriers on active threads. Non-running threads do not need to execute such barrier anyway, because these are implied by the scheduler context switches. Results in liburcu: Operations in 10s, 6 readers, 2 writers: memory barriers in reader: 1701557485 reads, 2202847 writes signal-based scheme: 9830061167 reads, 6700 writes sys_membarrier: 9952759104 reads, 425 writes sys_membarrier (dyn. check): 7970328887 reads, 425 writes The dynamic sys_membarrier availability check adds some overhead to the read-side compared to the signal-based scheme, but besides that, sys_membarrier slightly outperforms the signal-based scheme. However, this non-expedited sys_membarrier implementation has a much slower grace period than signal and memory barrier schemes. Besides diminishing the number of wake-ups, one major advantage of the membarrier system call over the signal-based scheme is that it does not need to reserve a signal. This plays much more nicely with libraries, and with processes injected into for tracing purposes, for which we cannot expect that signals will be unused by the application. An expedited version of this system call can be added later on to speed up the grace period. Its implementation will likely depend on reading the cpu_curr()->mm without holding each CPU's rq lock. This patch adds the system call to x86 and to asm-generic. [1] http://urcu.so membarrier(2) man page: MEMBARRIER(2) Linux Programmer's Manual MEMBARRIER(2) NAME membarrier - issue memory barriers on a set of threads SYNOPSIS #include <linux/membarrier.h> int membarrier(int cmd, int flags); DESCRIPTION The cmd argument is one of the following: MEMBARRIER_CMD_QUERY Query the set of supported commands. It returns a bitmask of supported commands. MEMBARRIER_CMD_SHARED Execute a memory barrier on all threads running on the system. Upon return from system call, the caller thread is ensured that all running threads have passed through a state where all memory accesses to user-space addresses match program order between entry to and return from the system call (non-running threads are de facto in such a state). This covers threads from all pro=E2=80=90 cesses running on the system. This command returns 0. The flags argument needs to be 0. For future extensions. All memory accesses performed in program order from each targeted thread is guaranteed to be ordered with respect to sys_membarrier(). If we use the semantic "barrier()" to represent a compiler barrier forcing memory accesses to be performed in program order across the barrier, and smp_mb() to represent explicit memory barriers forcing full memory ordering across the barrier, we have the following ordering table for each pair of barrier(), sys_membarrier() and smp_mb(): The pair ordering is detailed as (O: ordered, X: not ordered): barrier() smp_mb() sys_membarrier() barrier() X X O smp_mb() X O O sys_membarrier() O O O RETURN VALUE On success, these system calls return zero. On error, -1 is returned, and errno is set appropriately. For a given command, with flags argument set to 0, this system call is guaranteed to always return the same value until reboot. ERRORS ENOSYS System call is not implemented. EINVAL Invalid arguments. Linux 2015-04-15 MEMBARRIER(2) Signed-off-by: NMathieu Desnoyers <mathieu.desnoyers@efficios.com> Reviewed-by: NPaul E. McKenney <paulmck@linux.vnet.ibm.com> Reviewed-by: NJosh Triplett <josh@joshtriplett.org> Cc: KOSAKI Motohiro <kosaki.motohiro@jp.fujitsu.com> Cc: Steven Rostedt <rostedt@goodmis.org> Cc: Nicholas Miell <nmiell@comcast.net> Cc: Ingo Molnar <mingo@redhat.com> Cc: Alan Cox <gnomes@lxorguk.ukuu.org.uk> Cc: Lai Jiangshan <laijs@cn.fujitsu.com> Cc: Stephen Hemminger <stephen@networkplumber.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Peter Zijlstra <peterz@infradead.org> Cc: David Howells <dhowells@redhat.com> Cc: Pranith Kumar <bobby.prani@gmail.com> Cc: Michael Kerrisk <mtk.manpages@gmail.com> Cc: Shuah Khan <shuahkh@osg.samsung.com> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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- 11 9月, 2015 1 次提交
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由 Christoph Hellwig 提交于
Almost everyone implements dma_set_mask the same way, although some time that's hidden in ->set_dma_mask methods. This patch consolidates those into a common implementation that either calls ->set_dma_mask if present or otherwise uses the default implementation. Some architectures used to only call ->set_dma_mask after the initial checks, and those instance have been fixed to do the full work. h8300 implemented dma_set_mask bogusly as a no-ops and has been fixed. Unfortunately some architectures overload unrelated semantics like changing the dma_ops into it so we still need to allow for an architecture override for now. [jcmvbkbc@gmail.com: fix xtensa] Signed-off-by: NChristoph Hellwig <hch@lst.de> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Russell King <linux@arm.linux.org.uk> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Cc: Michal Simek <monstr@monstr.eu> Cc: Jonas Bonn <jonas@southpole.se> Cc: Chris Metcalf <cmetcalf@ezchip.com> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Ingo Molnar <mingo@elte.hu> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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