1. 26 4月, 2016 8 次提交
  2. 26 2月, 2016 3 次提交
    • S
      drm/fsl-dcu: mask all interrupts on initialization · 638c93f6
      Stefan Agner 提交于
      The state of the interrupt mask register on initialization is
      unknown, e.g. U-Boot could already used the DCU. So depending on
      the boot loader, the outcome of the interrupt mask register could
      be different. A defined state is much more preferable. Also, there
      is no value in keeping interrupts enabled which we don't need.
      Therefor, mask all interrupts on initialization.
      Signed-off-by: NStefan Agner <stefan@agner.ch>
      638c93f6
    • S
      drm/fsl-dcu: remove regmap return value checks · e291d298
      Stefan Agner 提交于
      It is not common to do regmap return value checks, especially not
      for memory mapped device. We can rule out most error returns since
      the conditions are static and we know they are ok (e.g. offset
      aligned to register stride). Also without proper error handling
      they are not really valuable for the user. Hence remove most of
      them.
      
      The check in the interrupt handler is worth keeping since a
      volatile register won't be readable in case register caching is
      still enabled.
      Signed-off-by: NStefan Agner <stefan@agner.ch>
      e291d298
    • S
      drm/fsl-dcu: specify volatile registers · efb8b491
      Stefan Agner 提交于
      Since we are using cached registers, we need to specify volatile
      registers explicitly to avoid reading their value from the cache.
      This allows to read the correct interrupt status in fsl_dcu_drm_irq
      and clear the asserted bits only.
      Signed-off-by: NStefan Agner <stefan@agner.ch>
      efb8b491
  3. 26 1月, 2016 1 次提交
  4. 15 12月, 2015 1 次提交
  5. 07 10月, 2015 1 次提交
  6. 06 10月, 2015 1 次提交
    • T
      drm/irq: Use unsigned int pipe in public API · 88e72717
      Thierry Reding 提交于
      This continues the pattern started in commit cc1ef118 ("drm/irq:
      Make pipe unsigned and name consistent"). This is applied to the public
      APIs and driver callbacks, so pretty much all drivers need to be updated
      to match the new prototypes.
      
      Cc: Christian König <christian.koenig@amd.com>
      Cc: Alex Deucher <alexander.deucher@amd.com>
      Cc: Russell King <rmk+kernel@arm.linux.org.uk>
      Cc: Inki Dae <inki.dae@samsung.com>
      Cc: Jianwei Wang <jianwei.wang.chn@gmail.com>
      Cc: Alison Wang <alison.wang@freescale.com>
      Cc: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
      Cc: Daniel Vetter <daniel.vetter@intel.com>
      Cc: Jani Nikula <jani.nikula@linux.intel.com>
      Cc: Philipp Zabel <p.zabel@pengutronix.de>
      Cc: David Airlie <airlied@linux.ie>
      Cc: Rob Clark <robdclark@gmail.com>
      Cc: Ben Skeggs <bskeggs@redhat.com>
      Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
      Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
      Cc: Mark Yao <mark.yao@rock-chips.com>
      Cc: Benjamin Gaignard <benjamin.gaignard@linaro.org>
      Cc: Vincent Abriou <vincent.abriou@st.com>
      Cc: Thomas Hellstrom <thellstrom@vmware.com>
      Signed-off-by: NThierry Reding <treding@nvidia.com>
      Reviewed-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      88e72717
  7. 20 8月, 2015 1 次提交
    • J
      drm/layerscape: Add Freescale DCU DRM driver · 109eee2f
      Jianwei Wang 提交于
      This patch add support for Two Dimensional Animation and Compositing
      Engine (2D-ACE) on the Freescale SoCs.
      
      2D-ACE is a Freescale display controller. 2D-ACE describes
      the functionality of the module extremely well its name is a value
      that cannot be used as a token in programming languages.
      Instead the valid token "DCU" is used to tag the register names and
      function names.
      
      The Display Controller Unit (DCU) module is a system master that
      fetches graphics stored in internal or external memory and displays
      them on a TFT LCD panel. A wide range of panel sizes is supported
      and the timing of the interface signals is highly configurable.
      Graphics are read directly from memory and then blended in real-time,
      which allows for dynamic content creation with minimal CPU
      intervention.
      
      The features:
      (1) Full RGB888 output to TFT LCD panel.
      (2) Blending of each pixel using up to 4 source layers
      dependent
      on size of panel.
      (3) Each graphic layer can be placed with one pixel resolution
      in either axis.
      (4) Each graphic layer support RGB565 and RGB888 direct colors
      without alpha channel and BGRA8888 BGRA4444 ARGB1555 direct
      colors
      with an alpha channel and YUV422 format.
      (5) Each graphic layer support alpha blending with 8-bit
      resolution.
      This is a simplified version, only one primary plane, one
      framebuffer, one crtc, one connector and one encoder for TFT
      LCD panel.
      Signed-off-by: NAlison Wang <b18965@freescale.com>
      Signed-off-by: NXiubo Li <lixiubo@cmss.chinamobile.com>
      Signed-off-by: NJianwei Wang <jianwei.wang.chn@gmail.com>
      Acked-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      109eee2f