Fix incorrect clock names for usb1, pcie1 and domain register
offset for pcie1 clock nodes on K2E EVM
Signed-off-by: NMurali Karicheri <m-karicheri2@ti.com>
Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>

The clocks tree for Keystone 2 NTCP devices should be
defined as following:
[refclk] - board dependent
 |- <papllclk> - PLL clock
    |- <paclk13> - fixed factor clock div=3 mul=1
       |- <clkpa> - gated clock
       |- <clkcpgmac> - gated clock
       |- <clksa> - gated clock

Hence, update Keystone 2 DT to follow HW specification.
Signed-off-by: NWingMan Kwok <w-kwok2@ti.com>
Signed-off-by: NGrygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>

Keystone2 Edison (K2E) is a Quad Cortex A15 based SoC with
1 DSP. It has standard peripherals such as i2c, spi, uart, timer,
pcie, etc similar to k2hk, but without wireless hardwares. This
patch add support for k2 Edison SoC and EVM. This re-uses the common
keystone.dtsi to include common bindings across the various k2
devices.
Signed-off-by: NMurali Karicheri <m-karicheri2@ti.com>
Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>