- 06 10月, 2014 1 次提交
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由 Robert Jarzmik 提交于
Fix the building of pxa clock drivers so that the files are actually compiled if and only if COMMON_CLK was selected by the architecture. This prevents conflicts with mach-pxa clock legacy implementation. Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 04 10月, 2014 2 次提交
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git://git.infradead.org/linux-mvebu由 Mike Turquette 提交于
clock mvebu changes for v3.18 (round 2) - armada 370/375 - Fix SSCG node lookup
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由 Mike Turquette 提交于
This reverts commit 9ff25d7b. Originally reported on the kernel-build-reports mailing list[0]. The problem is caused by kernel configs that select both pxa25x and pxa27x such as cm_x2xx_defconfig and palmz72_defconfig. The short term solution is to revert the patch introducing the failure. Longer term, all the PXA chips will be converted to the common clock framework allowing support for various PXA chips to build into a single image. Reverting just this one patch does introduce some dead code into the kernel, but that is offset by making it easier to convert the remaining PXA platforms to the clock framework. [0] http://lists.linaro.org/pipermail/kernel-build-reports/2014-October/005576.htmlSigned-off-by: NMike Turquette <mturquette@linaro.org>
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- 02 10月, 2014 1 次提交
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由 Mike Turquette 提交于
Merge tag 'v3.18-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Allow parent rate changes for i2s on rk3288 and rockchip as well as s3c24xx restart handlers.
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- 01 10月, 2014 13 次提交
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由 Heiko Stübner 提交于
S3C2412, S3C2443 and their derivatives contain a special software-reset register in their system-controller. Therefore register a restart handler for those. Tested on a s3c2416-based board, s3c2412 compile-tested. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Signed-off-by: NGuenter Roeck <linux@roeck-us.net>
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由 Heiko Stübner 提交于
Add infrastructure to write the correct value to the restart register and register the restart notifier for both rk3188 (including rk3066) and rk3288. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Signed-off-by: NGuenter Roeck <linux@roeck-us.net>
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由 Heiko Stuebner 提交于
Immutable branch with restart handler patches for v3.18
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由 Jianqun 提交于
The relation of i2s nodes as follows: i2s_src 0 0 594000000 0 i2s_frac 0 0 11289600 0 i2s_pre 0 0 11289600 0 sclk_i2s0 0 0 11289600 0 i2s0_clkout 0 0 11289600 0 hclk_i2s0 1 1 99000000 0 sclk_i2s0 is the master clock, when to set rate of sclk_i2s0, should allow to set its parent's rate, by add flag CLK_SET_RATE_PARENT for "i2s_frac", "i2s_pre", "i2s0_clkout" and "sclk_i2s0". Tested on rk3288 board using max98090, with command "aplay <music.wav>" Change-Id: I12faad082566532b65a7de8c0a6845e1c17870e6 Signed-off-by: NJianqun <jay.xu@rock-chips.com> Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
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由 Mike Turquette 提交于
Refine the definition around clk_ignore_unused, which caused some confusion recently on the linux-fbdev and linux-arm-kernel mailing lists[0]. [0] http://lkml.kernel.org/r/<20140929135358.GC30998@ulmo> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Mike Turquette 提交于
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由 Robert Jarzmik 提交于
Transition the PXA27x CPUs to the clock framework. This transition still enables legacy platforms to run without device tree as before, ie relying on platform data encoded in board specific files. Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Robert Jarzmik 提交于
Add the clock tree description for the PXA27x based boards. Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Robert Jarzmik 提交于
Move pxa27x clock drivers from arch/arm/mach-pxa to driver/clk. In the move : - convert to new clock framework legacy clocks - provide clocks as before for platform data based boards - provide clocks through devicetree Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Robert Jarzmik 提交于
Add missing bits for CCCR and CCSR : - CPLL and PPLL selection, either full speed or 13MHz - CPSR masks Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Robert Jarzmik 提交于
Document the device-tree binding of Marvell PXA based SoCs. PXA clocks are mostly fixed rate and fixed ratio clocks derived from an external oscillator, and gated by a register set (CKEN or CKEN*). Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Robert Jarzmik 提交于
Add a the common code used by all PXA variants. This is the first step in the transition from architecture defined clocks (in arch/arm/mach-pxa) towards clock framework. The goal is to have the same features (and not all the features) of the existing clocks, and enable the transition of PXA to device-tree. All PXA rely on a "CKEN" type clock, which : - has a gate (bit in CKEN register) - is generated from a PLL, generally divided - has an alternate low power clock Each variant will specialize the CKEN clock : - pxa25x have no low power clock - pxa27x in low power use always the 13 MHz ring oscillator - pxa3xx in low power have specific dividers for each clock The device-tree provides a list of CLK_* (ex: CLK_USB or CLK_I2C) to get a handle on the clock. While pxa-clock.h will describe all the clocks of all the variants, each variant will only use a subset of it. Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Mark Brown 提交于
The gpio-gate clock uses the gpiod_ APIs but does not directly include the header for them causing build failures in some configurations including ARM allnoconfig. Include the header directly. Signed-off-by: NMark Brown <broonie@kernel.org> Acked-by: NJyri Sarha <jsarha@ti.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 30 9月, 2014 2 次提交
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由 Mike Turquette 提交于
Merge tag 'for_3.18/samsung-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tfiga/samsung-clk into clk-next Samsung clock patches for v3.18 1) non-critical fixes (without the need to push to stable) fa0111be clk: samsung: exynos4: remove duplicate div_core2 divider clock instantiation b511593d clk: samsung: exynos4: fix g3d clocks c1425430 clk: samsung: exynos4: add missing smmu_g2d clock and update comments 22842d24 clk: samsung: exynos5260: fix typo in clock name e82ba578 clk: samsung: exynos3250: fix width field of mout_mmc0/1 59037b92 clk: samsung: exynos3250: fix width and shift of div_spi0_isp clock 5ce37f26 clk: samsung: exynos3250: fix mout_cam_blk parent list 2) Clock driver extensions 07ccf02b dt-bindings: clk: samsung: Document the DMC domain of Exynos3250 CMU d0e73eaf ARM: dts: exynos3250: Add CMU node for DMC domain clocks e3c3f19b clk: samsung: exynos3250: Register DMC clk provider 4676f0aa clk: samsung: exynos4: add support for MOUT_HDMI and MOUT_MIXER clocks
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由 Mike Turquette 提交于
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- 29 9月, 2014 6 次提交
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由 Peter Ujfalusi 提交于
It is safe to call the pm sync calls in interrupt context in this driver. Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: NTero Kristo <t-kristo@ti.com>
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由 Behan Webster 提交于
As written, the __init for ti_clk_get_div_table is in the middle of the return type. The gcc documentation indicates that section attributes should be added to the end of the function declaration: extern void foobar (void) __attribute__ ((section ("bar"))); However gcc seems to be very permissive with where attributes can be placed. clang on the other hand isn't so permissive, and fails if you put the section definition in the middle of the return type: drivers/clk/ti/divider.c:298:28: error: expected ';' after struct static struct clk_div_table ^ ; drivers/clk/ti/divider.c:298:1: warning: 'static' ignored on this declaration [-Wmissing-declarations] static struct clk_div_table ^ drivers/clk/ti/divider.c:299:9: error: type specifier missing, defaults to 'int' [-Werror,-Wimplicit-int] __init *ti_clk_get_div_table(struct device_node *node) ~~~~~~ ^ drivers/clk/ti/divider.c:345:9: warning: incompatible pointer types returning 'struct clk_div_table *' from a function with result type 'int *' [-Wincompatible-pointer-types] return table; ^~~~~ drivers/clk/ti/divider.c:419:9: warning: incompatible pointer types assigning to 'const struct clk_div_table *' from 'int *' [-Wincompatible-pointer-types] *table = ti_clk_get_div_table(node); ^ ~~~~~~~~~~~~~~~~~~~~~~~~~~ 3 warnings and 2 errors generated. By convention, most of the kernel code puts section attributes between the return type and function name. In the case where the return type is a pointer, it's important to place the '*' on left of the __init. This updated code works for both gcc and clang. Signed-off-by: NBehan Webster <behanw@converseincode.com> Reviewed-by: NMark Charlebois <charlebm@gmail.com> Reviewed-by: NFelipe Balbi <balbi@ti.com> Signed-off-by: NTero Kristo <t-kristo@ti.com>
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I "forgot" to update the dtb and the kernel crashed: |Unable to handle kernel NULL pointer dereference at virtual address 0000002e |PC is at __clk_get_flags+0x4/0xc |LR is at ti_dt_clockdomains_setup+0x70/0xe8 because I did not have the clock nodes. of_clk_get() returns an error pointer which is not checked here. Acked-by: NNishanth Menon <nm@ti.com> Signed-off-by: NSebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: NTero Kristo <t-kristo@ti.com>
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由 Tero Kristo 提交于
of_clk_add_provider makes an internal copy of the parent_names property while its called, thus it is no longer needed after this call and can be freed. Signed-off-by: NTero Kristo <t-kristo@ti.com> Cc: Mike Turquette <mturquette@linaro.org> Cc: Peter Ujfalusi <peter.ujfalusi@ti.com> Acked-by: NPeter Ujfalusi <peter.ujfalusi@ti.com>
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由 Tero Kristo 提交于
Previously, the TI clock driver initialized all the clocks hierarchically under each separate clock provider node. Now, each clock that requires IO access will instead check their parent node to find out which IO range to use. This patch allows the TI clock driver to use a few new features provided by the generic of_clk_init, and also allows registration of clock nodes outside the clock hierarchy (for example, any external clocks.) Signed-off-by: NTero Kristo <t-kristo@ti.com> Cc: Mike Turquette <mturquette@linaro.org> Cc: Paul Walmsley <paul@pwsan.com> Cc: Tony Lindgren <tony@atomide.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Peter Ujfalusi <peter.ujfalusi@ti.com> Cc: Jyri Sarha <jsarha@ti.com> Cc: Stefan Assmann <sassmann@kpanic.de> Acked-by: NTony Lindgren <tony@atomide.com>
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git://github.com/hisilicon/linux-hisi由 Mike Turquette 提交于
Hisilicon HiX5HD2 clock updates for 3.18-v2 - Add I2C clocks - Add watchdog clocks - Add sd clocks - Add complex clock implementation to support sata, usb and ethernet
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- 28 9月, 2014 7 次提交
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由 Wei Yan 提交于
hix5hd2 add I2C clocks (I2C0~i2C5) Signed-off-by: NWei Yan <sledge.yanwei@huawei.com> Signed-off-by: NZhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: NWei Xu <xuwei5@hisilicon.com>
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由 Guoxiong Yan 提交于
hix5hd2 add watchdog0 clocks Signed-off-by: NGuoxiong Yan <yanguoxiong@huawei.com> Signed-off-by: NZhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: NWei Xu <xuwei5@hisilicon.com>
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由 Jiancheng Xue 提交于
Signed-off-by: NJiancheng Xue <xuejiancheng@huawei.com> Signed-off-by: NZhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: NWei Xu <xuwei5@hisilicon.com>
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由 Zhangfei Gao 提交于
Support clk of sata, usb and ethernet Signed-off-by: NJiancheng Xue <xuejiancheng@huawei.com> Signed-off-by: NZhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: NWei Xu <xuwei5@hisilicon.com>
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由 Xiubo Li 提交于
Setting 'flags' to zero will be certainly a misleading way to avoid warning of 'flags' may be used uninitialized. uninitialized_var is a correct way because the warning is a false possitive. Signed-off-by: NXiubo Li <Li.Xiubo@freescale.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Mike Turquette 提交于
Merge tag 'sunxi-clocks-for-3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next Allwinner Clocks Additions for 3.18 The most important part of this serie is the addition of the phase API to handle the MMC clocks in the Allwinner SoCs. Apart from that, the A23 gained a new mbus driver, and there's a fix for a incorrect divider table on the APB0 clock.
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由 Mike Turquette 提交于
Merge tag 'v3.18-rockchip-cpuclk' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next CPU clock handling for Rockchip SoCs
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- 27 9月, 2014 8 次提交
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由 Heiko Stuebner 提交于
This adds the necessary soc-specific divider values and switches the armclk to use the newly introduced cpuclk type. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Reviewed-by: NDoug Anderson <dianders@chromium.org> Tested-by: NDoug Anderson <dianders@chromium.org>
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由 Heiko Stuebner 提交于
When changing the armclk on Rockchip SoCs it is supposed to be reparented to an alternate parent before changing the underlying pll and back after the change. Additionally there exist clocks that are very tightly bound to the armclk whose divider values are set according to the armclk rate. Add a special clock-type to handle all that. The rate table and divider values will be supplied from the soc-specific clock controllers. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Reviewed-by: NDoug Anderson <dianders@chromium.org> On a rk3288-board: Tested-by: NDoug Anderson <dianders@chromium.org>
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由 Heiko Stuebner 提交于
Rockchip SoCs contain clocks tightly bound to the armclk, where the best rate / divider is supplied by the vendor after careful measuring. Often this ideal rate may be greater than the current rate. Therefore prevent the ccf from trying to set these dividers itself by setting them to read-only. In the case of the rk3066, this also includes the aclk_cpu, which makes it necessary to also split its direct child-clocks (pclk_cpu, hclk_cpu, ...) into individual definitions for rk3066 and rk3188. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Reviewed-by: NDoug Anderson <dianders@chromium.org> Tested-by: NDoug Anderson <dianders@chromium.org>
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由 Heiko Stuebner 提交于
aclk_cpu_pre on the rk3188 can either be sourced from the armclk or the gpll. To reduce complexity on apll changes caused by cpufreq, reparent it always to the gpll source. If really necessary it could be reparented back on a per board level using the assigned-clocks mechanism. Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
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由 Jianqun 提交于
In RK3288, APLL lock status bit is in GRF_SOC_STATUS1, but in RK3188, is GRFSOC_STATUS0. Signed-off-by: NJianqun <jay.xu@rock-chips.com> Also name the constant accordingly as GRF_SOC_STATUS1 to prevent confusion. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Reviewed-by: NDoug Anderson <dianders@chromium.org> Tested-by: NDoug Anderson <dianders@chromium.org>
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由 Heiko Stuebner 提交于
The register providing the pll lock status is at a different address on the rk3066. The error became apparent while working on cpufreq support for the rockchip SoCs. Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
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由 Doug Anderson 提交于
The Rockchip PLL code switches into slow mode (AKA bypass more AKA 24MHz mode) before actually changing the PLL. This keeps anyone from using the PLL while it's changing. However, in all known Rockchip SoCs nobody should ever see the 24MHz when changing the PLL supplying the armclk because we should reparent children to an alternate (faster than 24MHz) PLL. One problem is that the code to switch to an alternate parent was running in PRE_RATE_CHANGE. ...and the code to switch to slow mode was _also_ running in PRE_RATE_CHANGE. That meant there was no real guarantee that we would switch to an alternate parent before switching to 24MHz mode. Let's move the switch to "slow mode" straight into rockchip_rk3066_pll_set_rate(). That means we're guaranteed that the 24MHz is really a last-resort. Note that without this change on real systems we were the code to switch to an alternate parent at 24MHz. In some older versions of that code we'd appy a (temporary) / 5 to the 24MHz causing us to run at 4.8MHz. That wasn't enough to service USB interrupts in some cases and could lead to a system hang. Signed-off-by: NDoug Anderson <dianders@chromium.org> Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
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由 Heiko Stuebner 提交于
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