1. 03 5月, 2007 1 次提交
    • M
      PCI: Flush MSI-X table writes · 988cbb15
      Mitch Williams 提交于
      This patch fixes a kernel bug which is triggered when using the
      irqbalance daemon with MSI-X hardware.
      
      Because both MSI-X interrupt messages and MSI-X table writes are posted,
      it's possible for them to cross while in-flight.  This results in
      interrupts being received long after the kernel thinks they're disabled,
      and in interrupts being sent to stale vectors after rebalancing.
      
      This patch performs a read flush after writes to the MSI-X table for
      mask and unmask operations.  Since the SMP affinity is set while
      the interrupt is masked, and since it's unmasked immediately after,
      no additional flushes are required in the various affinity setting
      routines.
      
      This patch has been validated with (unreleased) network hardware which
      uses MSI-X.
      
      Revised with input from Eric Biederman.
      Signed-off-by: NMitch Williams <mitch.a.williams@intel.com>
      Acked-by: N"Eric W. Biederman" <ebiederm@xmission.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      988cbb15
  2. 01 5月, 2007 11 次提交
  3. 30 4月, 2007 28 次提交