Signed-off-by: NJon Medhurst <tixy@yxit.co.uk>
Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>

The MRS instruction should set mode and interrupt bits in the read value
so it is simpler to use a new simulation routine (simulate_mrs) rather
than some modified emulation.

prep_emulate_rd12 is now unused and removed.
Signed-off-by: NJon Medhurst <tixy@yxit.co.uk>
Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>

We need to reject probing of instructions which read SPSR because
we can't handle this as the value in SPSR is lost when the exception
handler for the probe breakpoint first runs.

This patch also fixes the bitmask for MRS instructions decoding to
include checking bits 5-7.
Signed-off-by: NJon Medhurst <tixy@yxit.co.uk>
Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>

Emulation of instructions like "ADD rd, rn, #<const>" would result in a
corrupted value for rd.
Signed-off-by: NJon Medhurst <tixy@yxit.co.uk>
Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>

Probing these instructions was corrupting R0 because the emulation code
didn't account for the fact that they don't write a result to a
register.
Signed-off-by: NJon Medhurst <tixy@yxit.co.uk>
Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>

Now we have the framework code handling conditionally executed
instructions we can remove redundant checks in individual simulation
routines.
Signed-off-by: NJon Medhurst <tixy@yxit.co.uk>
Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>

When a kprobe is placed onto conditionally executed ARM instructions,
many of the emulation routines used to single step them produce corrupt
register results. Rather than fix all of these cases we modify the
framework which calls them to test the relevant condition flags and, if
the test fails, skip calling the emulation code.
Signed-off-by: NJon Medhurst <tixy@yxit.co.uk>
Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>

Currently emulate_ldrd and emulate_strd don't even have the adjustment
of the PC value, so in case of Rn == PC, it will not update the PC
incorrectly but instead load/store from the wrong address.  Let's add
both the adjustment of the PC value and the check for PC == PC.
Signed-off-by: NViktor Rosendahl <viktor.rosendahl@nokia.com>
Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>

Commit 6845664a(arm: Cleanup the irq namespace) introduces a typo
causing a build failure for the versatile platform.

[ tglx: Sorry, my bad. Have no idea how I fatfingered that ]
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: linux-arm-kernel@lists.infradead.org
LKML-Reference: <20110330060229.27397.7628.stgit@ponder>
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>

Use irq_set_chip_and_handler() instead. Converted with coccinelle.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>

Reorder 
irq_set_chip()
irq_set_chip_data()
irq_set_handler()

to

irq_set_chip()
irq_set_handler()
irq_set_chip_data()

so the next patch can combine irq_set_chip() and irq_set_handler() to
irq_set_chip_and_handler().

Automated conversion with coccinelle.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>

Convert to the new function names. Automated with coccinelle.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>

Use the generic version and just keep the arch specific output.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>

Remove the obsolete desc_handle_irq() helper.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>

Signed-off-by: NThomas Gleixner <tglx@linutronix.de>

Avoid the whole lazy disable dance in the demux handler by providing a
irq_disable() callback.

Use the proper accessor functions and tidy up gpio_irq_handler()
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>

Make use of the new functionality which ensures that irq_set_type is
called with the chip masked. Unmask is only done when the interrupt is
not disabled.

Retrieve the trigger type from irq_data in unmask
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>

No need to write the flow type. Core code does already.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>

Signed-off-by: NThomas Gleixner <tglx@linutronix.de>

Signed-off-by: NThomas Gleixner <tglx@linutronix.de>

Signed-off-by: NThomas Gleixner <tglx@linutronix.de>

Signed-off-by: NThomas Gleixner <tglx@linutronix.de>

1) Core code stores the flow type already
2) Flow type is accessible in irq_data
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>

Store the enabled mask in the local state, so there is no need to
fiddle in the irq descriptor.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>

Signed-off-by: NThomas Gleixner <tglx@linutronix.de>

Signed-off-by: NThomas Gleixner <tglx@linutronix.de>

Use the proper wrappers and use the flow type in irq_data.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>

Signed-off-by: NThomas Gleixner <tglx@linutronix.de>

Use the proper accessor function instead of fiddling in the status
bits directly.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Cc: linux-arm-kernel@lists.infradead.org

Remove the open coded access to irq_desc which will fail on sparse irq
and use the proper wrappers.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>

The core code handles thees already.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Cc: Colin Cross <ccross@android.com>
Cc: linux-tegra@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org

The conversion missed, that one of the irq functions is called from
the init code. Split it out, so the irq number based call works.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>

Signed-off-by: NThomas Gleixner <tglx@linutronix.de>

The machine id cleanup missed to remove the checks for now removed
ids.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>

commit 9eac6d0a (ARM: Remove dependency of plat-orion GPIO code on mach
directory includes) missed to convert one instance of
DOVE_GPIO_VIRT_BASE and left the orion_gpio_init() in mpp.c

Fix it up.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>

That wants to be AT91_SDRAMC0
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>

This clocksource function needs to be void.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>

The id removal left this machine check in which breaks the build on
some platforms. Remove it.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>

MFD changes in 4ec1b54c ('mfd: mfd_cell is now implicitly available to
mc13xxx drivers') changed the mc13xxx_platform_data struct layout.

At the time all users were changed, but this driver was introduced in
another tree at the same time.  This updates the mc13xxx_platform_data
user, fixing a build error.
Signed-off-by: NAndres Salomon <dilinger@queued.net>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

The inline assembly differences for v6 vs. v7 are purely
optimizations. On a v7 processor, an mrc with the pc sets the
condition codes to the 28-31 bits of the register being read. It
just so happens that the TX/RX full bits the DCC support code is
testing for are high enough in the register to be put into the
condition codes. On a v6 processor, this "feature" isn't
implemented and thus we have to do the usual read, mask, test
operations to check for TX/RX full. Thus, we can drop the v7
implementation and just use the v6 implementation for both.

Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>