Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Unit names come from the Android GK20A driver.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Change from traces of a newer binary driver version.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Change from traces of a newer binary driver version.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Bug noticed vs traces.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Differences noted vs traces.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Change from traces of a newer binary driver version.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Bug noticed vs traces.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Upcoming mobile Kepler GPUs (such as GK20A) use the platform bus instead
of PCI to which Nouveau is tightly dependent. This patch allows Nouveau
to handle platform devices by:

- abstracting PCI-dependent functions that were typically used for
  resource querying and page mapping,
- introducing a nv_device_is_pci() function that allows to make
  PCI-dependent code conditional,
- providing a nouveau_drm_platform_probe() function that takes a GPU
  platform device to be probed.

Core code as well as engine/subdev drivers are updated wherever possible
to make use of these functions. Some older drivers are too dependent on
PCI to be properly updated, but all newer code on which future chips may
depend should at least be runnable with platform devices.
Signed-off-by: NAlexandre Courbot <acourbot@nvidia.com>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Signed-off-by: NIlia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Signed-off-by: NIlia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Commit ea7dce90 ("drm/nv50/gr: print mpc trap name when it's not an mp
trap") added an nv_error call that was missing the priv parameter. This
causes GPFs if the error is ever hit.
Signed-off-by: NIlia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Signed-off-by: NIlia Mirkin <imirkin@alum.mit.edu>

Signed-off-by: NIlia Mirkin <imirkin@alum.mit.edu>

Also avoids printing the errors bitfield if that information has already
been shown.
Signed-off-by: NIlia Mirkin <imirkin@alum.mit.edu>

Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Compute code in mesa triggers one of these, hanging the engine.  Let's
at least ack the request for now to avoid the hang.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Fixes HUB_INIT timeout on GK110/GK208 when not using NVIDIA's ucode.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Need. A. Compiler...
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

If the initial data element is 0, it will never be written, even
though the value from the previous method may be there.
Signed-off-by: NKelly Doran <kel.p.doran@gmail.com>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

We care about the upper 32 bits here so we have to use 1ULL instead of 1
to avoid a shift wrapping bug.
Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: NMaarten Lankhorst <maarten.lankhorst@canonical.com>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Internal use only at this point.  Userspace later.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

NV1A is numerically higher than NV17 but generationally lower. Use the
new card type to help disambiguate.
Signed-off-by: NIlia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Signed-off-by: NIlia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

"drm/nve0-/gr: some new gpc registers can have multiple copies"
5ee86c41 caused a regression for nvc0, because the bit indicating last
transfer has occured was no longer set, resulting in random system lockups.
Reported-by: NRonald Uitermark <ronald645@gmail.com>
Tested-by: NRonald Uitermark <ronald645@gmail.com>
Signed-off-by: NMaarten Lankhorst <maarten.lankhorst@canonical.com>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

NVC1/NVD9 are the only chipsets that should have anything different
happen on them after this.  We previously weren't doing these
register modifications, and NVIDIA do.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

This can be generalised and used on GK104 (probably even GF117), but lets
just make it work for now.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Signed-off-by: NBen Skeggs <bskeggs@redhat.com>