As of commit bb475230 ("reset: make optional functions really
optional"), the reset framework API calls use NULL pointers to describe
optional, non-present reset controls.

This allows to return errors from devm_reset_control_get_optional and to
call reset_control_(de)assert unconditionally.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

We only need to call sunxi_nfc_wait_cmd_fifo_empty() if we want to send
a new command. Move the sunxi_nfc_wait_cmd_fifo_empty() call to right
place to avoid extra register reads.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

Some operations, like read/write an entire page of data with the ECC
engine enabled, are known to take a lot of time. Use the interrupt-based
waiting mode in these situation.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

wait_for_completion_timeout() returns 0 if a timeout occurred, 1
otherwise. Fix the sunxi_nfc_wait_events() accordingly.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

The driver is incorrectly assuming that the ECC block size is always 1k
which is not always true.

Also take the other cases into account.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Setup the maximum ECC config when NAND_ECC_MAXIMIZE is set.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

The NAND framework is now able to select the best NAND timings for us.
All we have to do is implement a ->setup_data_interface() function to
apply those timings and remove the timing selection code from the sunxi
driver.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

The code to initialize a struct nand_hw_control is duplicated across
several drivers. Factorize it using an inline function.
Signed-off-by: NMarc Gonzalez <marc_gonzalez@sigmadesigns.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

I moved the sanity check on ecc->size before the allocation so that we
don't leak memory on error.

Fixes: 05af074a4b73 ('mtd: nand: sunxi: check ecc->size values')
Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

The NAND controller on some sun8i chips needs its reset line to be
deasserted before they can enter working state.
Signed-off-by: NIcenowy Zheng <icenowy@aosc.xyz>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

Implement ecc->write_subpage() to prevent core code from assigning this
hook to nand_write_subpage_hwecc(). This default implementation tries
to call ecc->hwctl() which in our case is NULL, thus leading to a NULL
pointer dereference.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

Verify that the ecc->size value is either 512 or 1024 bytes.
This should always be the case if this field was assigned to the
nand->ecc_step_size_ds value, but can be wrong when the user overloaded
this value with the nand-ecc-step-size DT property.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

Switching to 1k ECC blocks when possible provides better resistance against
concentrated bitflips. Say you have those two configurations:

1/ 16bits/512bytes
2/ 32bits/1024bytes

Both of them require the same amount of ECC bytes (only true for this
specific engine), but the second config allows you to correct the case
where most of your bitflips are concentrated in a single 512bytes portion.

This fact makes the 1k ECC block size more advantageous than the 512bytes
one.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

The column address passed to the RNDOUT operation was missing the page
size offset.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Fixes: 614049a8 ("mtd: nand: sunxi: add support for DMA assisted operations")

In case of error, the function dmaengine_prep_slave_sg() returns NULL
pointer not ERR_PTR(). The IS_ERR() test in the return value check
should be replaced with NULL test.
Signed-off-by: NWei Yongjun <yongjun_wei@trendmicro.com.cn>
Fixes: 614049a8 ("mtd: nand: sunxi: add support for DMA assisted operations")
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

The sunxi NAND controller is able to pipeline ECC operations only when
operated in DMA mode, which improves a lot NAND throughput while keeping
CPU usage low.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

This value should not be part of nand_ecc_modes_t as it specifies
algorithm not a mode. We successfully managed to introduce new "algo"
field which is respected now.
Signed-off-by: NRafał Miłecki <zajec5@gmail.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

Implementing the mtd_ooblayout_ops interface is the new way of exposing
ECC/OOB layout to MTD users.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

Allow for NULL cur_offs values when the caller does not know where the
NAND page register pointer points to.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

sunxi_nfc_hw_ecc_read_chunk() always retrieves the ECC and protected free
bytes, no matter if the user really asked for it or not. This can take a
non negligible amount of time, especially on NAND chips exposing large OOB
areas (> 1KB). Make it optional.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

In order to support DMA operations in a clean way we need to extract some
of the logic coded in sunxi_nfc_hw_ecc_read/write_page() into their own
function.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

Some NAND operations are so fast that it doesn't make any sense to use
interrupt based waits (the scheduling overhead is not worth it).
Rename sunxi_nfc_wait_int() into sunxi_nfc_wait_events() and add a
parameter to specify whether polling should be used or not.

Note that all sunxi_nfc_wait_int() are moved to the polling approach now,
but this should change as soon as we have more information about the
approximate time we are about to wait (can be extracted from the NAND
timings, and the type of operation).
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

Replace open coded polling loops by readl_poll_timeout() calls.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

->dev_ready() is not supposed to wait for busy to ready solution (this is
the role of ->waitfunc()).
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

When the NAND controller operates in DMA mode it can pipeline ECC
operations which improves the throughput.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

mod and ahb clocks are not disabled when the NAND controller device is
removed.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

NFC_PAGE_SHIFT() already takes the real page_shift value and subtract 10
to it.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

NFC_ECC_ERR_CNT() is not taking into account the case when the NAND chip
contains more than 4 ECC blocks (NANDs with 4kB+ pages).
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

We don't need to manually toggle the CE line since the controller handles
it for us. Moreover, keeping the CE line low when interacting with a DDR
NAND can be problematic (data loss in some corner cases).
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

Try to pack address and command cycles into a single NAND controller
command to avoid polling the status register for each single change
on the NAND bus.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

Being able to read subpages can greatly improve read performances if the
MTD user is only interested in a small section of a NAND page.
This is particularly true with large pages (>= 8k).
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

Allwinner's ECC engine is capable of protecting a few bytes of the OOB
area. Implement specific OOB functions to benefit from this capability.

Also, when in raw mode, the randomizer is disabled, which means you'll
only be able to retrieve randomized data, which is not really useful
for most applications.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

Adapt the NAND controller clk rate to the tWB, tADL, tWHR and tRHW
timings instead of returning an error when the maximum clk divisor is
not big enough to provide an appropriate timing.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

The ONFI spec says that EDO should be enabled if the host drives tRC less
than 30ns, but the code just tests for the tRC_min value extracted from
the timings exposed by the NAND chip not the timings actually configured
in the NAND controller.
Fix that by first rounding down the requested clk_rate with
clk_round_rate() and then checking if tRC is actually smaller than 30ns.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

Unlike what is specified in the Allwinner datasheets, the NAND clock rate
is not equal to 2/T but 1/T. Fix the clock rate selection accordingly.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

sunxi_nand_chip_set_timings() is extracting a pointer to the nfc from the
nand->controller field, but this field is initialized after
sunxi_nand_chip_set_timings() call.
Reorder the calls to avoid any problem.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

Some drivers are including linux/of_mtd.h even if they don't use any of
the of_get_nand_xxx() helpers.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: NHarvey Hunt <harvey.hunt@imgtec.com>

mtd->priv is no longer pointing to the struct nand_chip it is attached to.
Replace those accesses by mtd_to_nand() calls.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Fixes: 4be4e03e ("mtd: nand: sunxi: add randomizer support")
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

Suggested-by: NRichard Weinberger <richard@nod.at>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Acked-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

Add support for the randomizer engine available in Allwinner's NFC IP.

Randomization is useful to support modern NAND chips which are sensitive to
repeated patterns. On such NANDs you might experience an unexpectedly high
number of bitflips when you repeat the same pattern all over a given NAND
block.
Randomizing input data mitigate this problem by avoiding such repeated
patterns.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>